• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.6
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• pp.851-858
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• 2012

In this paper, we design a seismic data acquisition system(SDAS) and implement it. This system is essential for development of a noble local earthquake disaster preventing system in population center. In the system, we choose a proper MEMS-type triaxial accelerometer as a sensor, and FPGA and ARM processor are used for implementing the system. In the SDAS, each module is realized by Verilog HDL and C Language. We carry out the ModelSim simulation to verify the performances of important modules. The simulation results show that the FPGA-based data acquisition module can guarantee an accurate time-synchronization for the measured data from each axis sensor. Moreover, the FPGA-ARM based embedded technology in system hardware design can reduce the system cost by the integration of data logger, communication sever, and facility control system. To evaluate the data acquisition performance of the SDAS, we perform experiments for real seismic signals with the exciter. Performances comparison between the acquired data of the SDAS and the reference sensor shows that the data acquisition performance of the SDAS is valid.

• Proceedings of the Korea Contents Association Conference
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• 2005.05a
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• pp.443-447
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• 2005

EMAST(Embedded Mobile Automatic System for Telematics) is implemented in SoC using the CAN and ARM Processor. For the general usage, EMAST must satisfy the two condition. First, Mobile internal interface is to be designed to support Differential Transceiver, Optical Transceiver and Wireless Transceiver Second, it should be supporting the interface between terminals using EMAST and telematics networks. In this paper, we propose EMAST structure and the efficient interface structure between EMAST and each mobile units.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.1042-1050
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• 2007

This paper describes the system which automatically generates power-minimized embedded cores from MDL descriptions. An automatic generation system is constructed which generated embedded cores which consumes less power for application programs. From the usage information on pipeline stages for each instruction, the proposed system generates embedded cores with the capability of detecting/resolving pipeline hazards. The generated cores are configured such that the power consumption is minimized. The proposed system has been tested by generating HDL codes for ARM9, MIPS R3000 architectures. Experimental results show functional accuracy of the generated cores, and show that power reduction of $20%{\sim}40%$ has been observed for benchmark programs.

• Journal of Welding and Joining
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• v.19 no.4
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• pp.429-436
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• 2001

The effect of welding condition on the microstructures of the weld metal in A7N01 welded by $CO_2$ laser was investigated. The number of ripples was increased with decreasing power and increasing welding speed. In the bead without ripple lines, the subgrain microstructures distribution from the fusion line toward the center of the bead were in the order of cellular, dendritic and equiaxed dendrite. However, in the bead with ripple lines, cellular and dendritic were formed between the fusion boundary and the ripple line. Inaddition, those structures were also observed between the ripple line. Equiaxed dendrites were formed only at the center line region. Cellular and dendritics formed near the ripple line were larger than those formed near the fusion boundary. The cooling rates estimated by the dendrite arm spacing were in the range of 200 to 1150oC/s. Cooling rate was increased with decreasing the power and increasing the welding speed. Mg and Zn segregated at the boundaries of cellulars and dendritics, Mg was segregated more than Zn. The segregation of Mg and Zn decreased with increasing cooling rate. Hardness of the weld metal was lower than that of the base metal in all welding conditions and increased as the cooling rate increased.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.980-985
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• 1988

In this paper, a control system of the PUMA 560 robot manipulator using a PC (Personal Computer) is presented. The hardware of the designed control system is composed of IBM-PC/AT, interface board, selection board, interrupt generating circuit, and the servo control unit of the PUMA controller. A robot control library is developed using assembly and C language, and is composed of several low-level functions and arm interface routines, world model routines, arm kinematics routines, and motion command service routines. Using the designed library, joint interpolated motion and Cartesian interpolated motion of the PUMA robot manipulator are realized. In the future, our system is expected to be a very helpful basis and a useful tool for developing various control algorithms of robot manipulator using sensory information.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.639-642
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• 2009

LN2440SBC 임베디드 보드는 ARM 코어 방식의 S3C2440A CPU를 가진 임베디드 컴퓨터 시스템이다. 이 시스템에 부착한 터치스크린 기능을 가진 TFT LCD 키트인 LP35의 구동을 위해서는 ARM 코어, LCD 컨트롤러, 그리고 LCD 장치와의 통신을 위한 SPI(serial peripheral interface)의 초기화와 LCD 화면에 이미지, 선, 도형 같은 것들의 출력을 가능하게 해주는 그래픽스 라이브러리 함수들이 필요하다. 본 논문은 이같은 기능들을 가지는 LP35를 위한 드라이버의 구현 방법을 기술한다. 특히, 드라이버 구동을 위한 초기화 방법과 화면 출력 기능들의 구현을 위해 필요한 픽셀 디스플레이 함수의 구현에 중점을 두어 설명한다. 또한 픽셀 디스플레이 함수를 이용한 기본 그래픽스 라이브러리 함수들에 대해 설명한다. 드라이버의 초기화를 위해서는 클럭 속도 설정, 범용 입출력 핀(GPIO)을 LCD와 SPI 용으로의 할당. SPI의 마스터/슬레이브 및 보오 레이트 설정, LCD 컨트롤러 레지스터 설정을 통한 LCD 기능 선택. 그리고 SPI를 통한 LCD 장치로의 파워 온(power on) 명령 전달 등이 수행된다.

• Journal of Korean Neurosurgical Society
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• v.51 no.3
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• pp.177-181
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• 2012

We present a case of an athetoid cerebral palsy with quadriparesis caused by kyphotic deformity of the cervical spine, severe spinal stenosis at the cervicomedullary junction, and atlantoaxial instability. The patient improved after the first surgery, which included a C1 total laminectomy and C-arm guided righ side unilateral C1-2 transarticular screw fixation. C1-2 fixation was not performed on the other side because of an aberrant and dominant vertebral artery (VA). Eight months after the first operation, the patient required revision surgery for persistent neck pain and screw malposition. We used intraoperative VA angiography with simultaneous fluoroscopy for precise image guidance during bilateral C1-2 transarticular screw fixation. Intraoperative VA angiography allowed the accurate insertion of screws, and can therefore be used to avoid VA injury during C1-2 transarticular screw fixation in comorbid patients with atlantoaxial deformities.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.229-236
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• 2005

This paper presents a system level architecture evaluation technique that leverages transaction level modeling but also significantly extends it to the realm of system level performance evaluation. A major issue lies with the modeling effort. To reduce the modeling effort the proposed technique develops the concept of worst case scenarios. Since the memory controller is often found to be an important component that critically affects the system performance and thus needs optimization, the paper further addresses how to evaluate and optimize the memory controllers, focusing on the test environment and the methodology. The paper also presents an industrial case study using a real state-of-the-art design. In the case study, it is reported that the proposed technique has helped successfully find the performance bottleneck and provide appropriate feedback on time.

• Clinical and Experimental Reproductive Medicine
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• v.16 no.1
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• pp.41-55
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• 1989

Lymphocyte chromosome preparations obtained by the micromethod (Arakaki and Sparkes, 1963) from 234 our patients (165 females and 69 males) were analysed by C-, NOR-and GC-bandings for chromosome heteromorphisms. The centromeric regions of chromosomes 1,9,16 and the long arm of the Y chromosomes were tested for C heteromorphism. Minor variations found in this study such as inv(9), prominant short arms and large satellites of acrocentrics were also examined by appropriate banding techniques. Of the 234 probands, a total of 125 different C-variants were detected, and the average frequency of the variants per individual was estimated to be 0.53. The observed variations were as follows : 99 qh variants, 5 pericentric inversions of chromosome 9, and 21 satellite and/or short arm variants.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.74-79
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• 2007

In general, the high cost, long time, and complex steps are required in the design and implementation of MPSoC(Multi-Processor System on a Chip), therefore a platform is used to test the functionality and performance of IPs(Intellectual Properties). In this paper, we study a platform architecture to verify IPs based on Interconnect Network among processors, and show that the MPSoC platform gives better performance than a single processor for an application program.