• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.512-514
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• 2007

The number of transformers and the size of transformers in inverter using 3-phase transformer could be reduced compare with a multi-level inverter using single phase transformer. but still the 3-phase transformer inverter needs many switches. In this study, we proposed the isolated multi-level inverter using 3-phase transformers and common arm. Also, the equal-area method is used to calculate conduction angle with switching frequency equal to output fundamental frequency and it can reduce harmonics component of output voltage and switching loss. Finally, We tested multi-level inverter to clarify electric circuit and reasonableness through Matlab simulation and experiment by using prototype inverter.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.880-882
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• 2005

소프트웨어 개발에 있어 가상 프로토타입의 활용은 하드웨어와의 병렬적인 개발 진행, 하드웨어 변경에 따른 신속한 대처, 확장된 디버깅과 벤치마킹 정보 등을 통해 개발 효율을 증대시킨다. 본 논문은 ARM을 기반하는 시스템의 소프트웨어 개발을 위한 가상 프로토타입 구현에 대해 다룬다. ARM사의 ADS1.2에서 제공하는 ARMulator의 Instruction Set Simulator를 기반하여 소프트웨어 개발자 관점의 추상화 수준으로 System-on-chip인 삼성 S3C2400의 축소된 형태를 가정하여 가상 프로토타입을 설계 및 구현하였다.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.242-244
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• 2019

본 논문은 방사선 치료에 사용되는 선형 전자가속기(LINAC)의 작동 원리와 구성 등 의료용 LINAC의 전반을 다룬다. 의료용 LINAC은 전자총에서 발사된 전자를 가속기 튜브 내에서 가속시켜 전자빔을 발생시키고, 이러한 전자빔을 금속 표적에 충돌시켜 발생한 X 선을 인체에 조사하는 원리이다. 최근에는 O-arm, C-arm 등 3-D 촬영을 위한 치료기가 개발됨에 따라, 의료용 LINAC의 전자총, 마그네트론 등을 구동하는데 사용되는 고전압 전원장치 또한 소형화와 고밀도화가 요구되는 추세이다. 본 논문에서는 마그네트론 구동을 위한 고밀도 40kV/100A 음극성 펄스 모듈레이터와 정전압 정전류 제어 및 50kV 절연이 가능한 히터 전원장치를 설계 및 제작하였으며, 9.3GHz, 1.7MW X-Band 마그네트론 연계실험을 통해 고효율 고신뢰성의 동작을 확인하였다.

• The Journal of Pediatrics of Korean Medicine
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• v.23 no.1
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• pp.95-113
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• 2009

Objectives This study was investigated to find how the orally administrated Moschus, herbal combination with Moschus, and herbal combination improves the rats' memory and rats' liver. These medications are generally known asthe memory improvement. Methods This study used the Sprague Dawley rats. They were divided into two groups - SD rats and orally administrated Saline(Control group). 0.473 mg/kg Moschus(HM-A), 153.9 mg/kg herbal composition without Moschus(HM-B), and 165.95 mg/kg herbal composition with Moschus combined(HM-C) Control, saline were orally administered. Each group was trained in the eight-arm radial maze task at the conditions of before oral administrated, and also right after third, sixth, and eighth by oral administration. Lastly, these animals were killed and were tested for brain tissue and serum AST/ALT level to measure how the medications were effected to the liver function. Results The result of radial eight-arm maze task test, the HM-B and HM-C groups showed significant decrease in mistakes from the fourth day of testing. Whereas, the HM-A group showed increasing in the error rate. HM-A and HM-C group of rats had significantly increased amount of acetylcholinesterase in the CA1 region of hippocampus, compared to the control group. Whereas, HM-B and HM-C group had increased level of ChAT compared to the control group. On the other hand, each experimental group did not show any significant difference to the level of serum AST/ALT and the weight ratio of the liver to the body. Conclusions This study provided evidences that the orally administered memory improvement herbal medication, and Moschus were effective to improve memory.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.11
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• pp.12-17
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• 2009

This paper presents a tag emulator for a UHF band RFID system. The tag emulator supports the 1800-6C and EPC global class 1 generation 2 standards. The transmitted signal from a reader is generated using the PIE coding and ASK modulation methods. Signals of a tag are from the FM0 coding and ASK modulation methods. The ARM7 processor carries out the overall control of the system and signal analysis of incoming data. The verification of the tag emulator employs the application platform implemented in C++. Users can define parameter values for protocol during the application run. The tag emulator presented in this paper allows evaluating various design alternatives of the target RFID system in real applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.447-457
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• 2004

This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25${\mu}{\textrm}{m}$, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10$0^{\circ}C$ and has about 36,639 gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9A
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• pp.931-939
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• 2007

This paper describes the system which automatically generates instruction-set simulators cores using the SMDL. SMDL describes structure and instruction-set information of a target DSP machine. Analyzing behavioral information of each pipeline stage of all instructions on a target ASIPS, the proposed system automatically generates a cycle-accurate instruction set simulator in C++ for a target processor. The proposed system has been tested by generating instruction-set simulators for ARM9E-S, ADSP-TS20x, and TMS320C2x architectures. Experiments were performed by checking the functions of the $4{\times}4$ matrix multiplication, 16-bit IIR filter, 32-bit multiplication, and the FFT using the generated simulators. Experimental results show the functional accuracy of the generated simulators.

• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.452-458
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• 2010

In case of an embedded system with computing resource restrictions such as system power and cpu, the overhead due to displaying data on the computer screen may have a significant influence on the system performance. This paper describes an initialization method for LCD-driving components such as an ARM Core, an LCD controller, and an SPI(serial peripheral interface). It also introduces a pixel display function and a panel display method using virtual screen for reducing the display overhead for an LN2440SBC system with an ARM9-based S3C2440A microprocessor. A virtual screen is a large space of computer memories allocated much larger than those needed for one-time display of an image. Displaying a specific region of a virtual screen is done by assigning it as a view-port region. Such a display is useful in an embedded system when concurrently running tasks produce and display their respective results on the screen; it is especially so when the execution result of each task is partially modified, instead of being totally modified, on its turn and displayed. If the tasks running on such a system divide and make efficient use of the region of the virtual screen, the display overhead can be minimized. For the performance comparison with and without using the virtual screen, two different images are displayed in turn and the amount of time consumed for their display is measured. The result shows that the display time of the former is about 5 times faster than that of the latter.

• The KIPS Transactions:PartA
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• v.18A no.1
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• pp.1-10
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• 2011

Physical modeling has been widely used for sound synthesis since it synthesizes high quality sound which is similar to real-sound for musical instruments. However, physical modeling requires a lot of parameters to synthesize a large number of sounds simultaneously for the musical instrument, preventing its real-time processing. To solve this problem, this paper proposes a single instruction, multiple data (SIMD) based multi-core processor that supports real-time processing of sound synthesis of gayageum which is a representative Korean traditional musical instrument. The proposed SIMD-base multi-core processor consists of 12 processing elements (PE) to control 12 strings of gayageum in which each PE supports modeling of the corresponding string. The proposed SIMD-based multi-core processor can generate synthesized sounds of 12 strings simultaneously after receiving excitation signals and parameters of each string as an input. Experimental results using a sampling reate 44.1 kHz and 16 bits quantization show that synthesis sound using the proposed multi-core processor was very similar to the original sound. In addition, the proposed multi-core processor outperforms commercial processors(TI's TMS320C6416, ARM926EJ-S, ARM1020E) in terms of execution time ($5.6{\sim}11.4{\times}$ better) and energy efficiency (about $553{\sim}1,424{\times}$ better).