• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.155-155
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• 2000

A high performance control and monitoring system for a high speed railway train requires a reliable the real-time communication network. TCN/WTB is designed for the data transmission over the train bus, and UIC556 defines that all the data be transmitted over TCN/WTB. This paper evaluates the performance of the link layer of WTB(Wired Train Bus). The evaluated results can be used for the selection of parameters for the sporadic message data.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.281-283
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• 2016

Recently, many industrial instruments face the problem of protocol compatibility with the external monitoring and control system. This paper is prepared in the main control board to support the industrial communication protocol conversion, control, and monitoring. The industrial communication gateway module is also designed to ensure that the protocol conversion of CAN bus and Ethernet. The main board processor is used the Atmega2560, and placed 4ea RS485 serial slots for sub-board. One of them is used for communication CAN bus and Ethernet. It provides analog and digital I / O through each of the slots is used for control and monitoring.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.4
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• pp.303-310
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• 2008

Recently, IEC 61850 supports the standardized communication technique in both station bus and process bus, and presents substation automation model. In order to implement the IEC 61850 based communication in a substation using the MU (merging unit) which is one of the important data acquisition equipments in substation automation, the time synchronization is demanded for cooperative operation between the devices. This paper proposes the precision time synchronization technique using IRIG-B protocol to develop the MU under IEC 61850 communication protocol. The proposed technique is implemented and its performance is verified experimentally.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.11
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• pp.1305-1317
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• 1999

NUMA 구조는 원격 메모리에 대한 접근이 불가피한 구조적 특성 때문에 상호 연결망이 성능을 좌우하는 큰 변수가 된다. 기존에 대중적으로 사용되던 버스는 물리적 확장성 및 대역폭에서 대규모 시스템을 구성하는 데 한계를 보인다. 이를 대체하는 고속의 지점간 링크를 사용한 링 구조는 버스가 가지는 확장성 및 대역폭의 한계라는 단점을 개선하였으나, 많은 클러스터가 연결되는 경우에는 전송 지연시간이 증가하는 문제점을 가지고 있다. 본 논문에서는 스누핑 프로토콜이 적용된 링 구조에서 클러스터 개수 증가에 따른 지연시간 증가의 문제점을 보완하기 위해 계층적 링 구조로의 확장을 제안하고, 이 구조에 효과적인 캐쉬 일관성 프로토콜을 설계하였다. 전역 링과 지역 링을 연결하는 브리지는 캐쉬 프로토콜을 관리하며 이 프로토콜에 의해 지역 링의 부하를 줄일 수 있도록 트랜잭션을 필터링하는 역할도 담당함으로써 시스템의 성능을 향상시킨다. probability-driven 시뮬레이터를 통해 계층적 링 구조가 시스템의 성능 및 링 이용률에 미치는 영향을 알아본다. Abstract Since NUMA architecture has to access remote memory, interconnection network performance determines performance of NUMA architecture. Bus, which has been used as popular interconnection network of NUMA, has a limit to build a large-scale system because of limited physical scalability and bandwidth. Ring interconnection network, composed of high-speed point-to-point link, made up for bus's defects of scalability and bandwidth. But, it also has problem of increasing delay as the number of clusters is increased. In this paper, we propose a hierarchical expansion of snoop-based ring architecture in order to overcome ring's defects of increasing delay. And we also design an efficient cache coherence protocol adopted to this architecture. Bridge, which connects local ring and global ring, maintains cache coherence protocol and does snoop-filtering which reduces local ring and cluster bus utilization. Therefore bridge can improve performance of this system. We analyze effects of hierarchical architecture on the performance of system and utilization of point-to-point links using probability-driven simulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.69-78
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• 2010

To implement the high performance SoC, we propose the flying master bus architecture that a specially defined master named as the flying master directly accesses the selected slaves with no regard to the bus protocol. The proposed bus architecture was implemented through Verilog and mapped the design into Hynix 0.18um technology. As master and slave wrappers have around 150 logic gate counts, the area overhead is still small considering the typical area of modules in SoC designs. In TLM performance simulation about proposed architecture, 25~40% of transaction cycle and 43~60% of bus efficiency are increased and 43~77% of request cycle is decreased, compared with conventional bus architecture. Conclusively, we assume that the proposed flying master bus architecture is promising as the leading candidate of the bus architecture in the aspect of performance and efficiency.

• Journal of IKEEE
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• v.23 no.3
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• pp.1096-1099
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• 2019

In this paper, we propose the protocol for construction of smart factory. The proposed protocol for construction of smart factory consists of an OPC UA Server/Client, a technology of TSN realtime communication, a NTP & PTP time synchronization protocol, a FieldBus protocol and conversion module, a technology of saving data for data transmit latency and synchronization protocol. OPC UA server/client is a system integration protocol which makes interface industrial hardware device and supports standardization which allows in all around area and also in not independent from any platform. A technology of TSN realtime communication provides an high sensitive time management and control technology in a way of sharing specific time between devices in the field of high speed network. NTP & PTP time synchronization protocol supports IEEE1588 standardization. A fieldbus protocol and conversion module provide an extendable connectivity by converting industrial protocol to OPC. A technology of saving data for data transmit latency and synchronization protocol provide a resolution function for a loss and latency of data. Results from testing agencies to assess the performance of proposed protocol for construction of smart factory, response time was 0.1367ms, synchronization time was 0.404ms, quantity of concurrent access was 100ea, quantity of interacting protocol was 5ea, data saving and synchronization was 1,000 nodes. It produced the same result as the world's highest level.

• ETRI Journal
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• v.32 no.5
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• pp.713-721
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• 2010

E-textile technology has earned a great deal of interest in many fields; however, existing wearable network protocols are not optimized for use with conductive yarn. In this paper, some of the basic properties of conductive textiles and requirements on wearable personal area networks (PANs) are reviewed. Then, we present a wearable personal network (WPN), which is a four-layered wearable PAN using bus topology. We have designed the WPN to be a lightweight protocol to work with a variety of microcontrollers. The profile layer is provided to make the application development process easy. The data link layer exchanges frames in a master-slave manner in either the reliable or best-effort mode. The lower part of the data link layer and the physical layer of WPN are made of a fabric serial-bus interface which is capable of measuring bus signal properties and adapting to medium variation. After a formal verification of operation and performances of WPN, we implemented WPN communication modules (WCMs) on small flexible printed circuit boards. In order to demonstrate the behavior of our WPN on a textile, we designed a WPN tutorial shirt prototype using implemented WCMs and conductive yarn.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.7
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• pp.1256-1271
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• 1994

In this paper a GFC protocol based on HMR(High-speed Multimedia Ring) with a dynamic quota allocation is proposed and the performance of proposed protocol is evaluated by simulation. The HMR a medium access protocol proposed for Gbit ATM-LAN, can be applied to the GFC protocol without any modification because it uses only 4 bits for medium access of several topologies such as bus, ring and stared-bus, and priority control for satisfaction of different QoS(Quality of Service) requirements. The quota allocation method of HMR called static quota allocation has a problem of excessive access delay for the traffic with high burstness. In this paper a dynamic quota allocation method which allocates quota to the nodes according to the queue length is proposed and the performance of HMR with dynamic quota allocation is evaluated by seven simulation scenarios of CCITT. The HMR with proposed method shows better shows better access delay characteristics than the HMR with static quota allocation. Also the simulation results show that access delay performance of HMR is better than that of ATMR proposed by Japan and is similar to that of DQDB proposed by Australia.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.290-290
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• 2000

This paper presents some ideas about an open architectural controller platform for semiconductor manufacturing equipment First, we proposed modular-typed software architecture. Each module is composed of commands and status sets. Second, common bus protocol is suggested in order to communicate with other modules. It is designed with visual c++ programming. Finally, job program is consisted of simple commands and status. Consequently, Controllers are easily developed with some required modular assembling.

• ETRI Journal
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• v.10 no.3
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• pp.83-91
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• 1988

This paper describes the architecture and the performance analysis of a multiprocessor system, which is based on the shared memory and single system bus. The system bus provides the pended protocol for the multiprocessor environment. Analyzing the processor utilization, address/data bus utilization and memory conflicts, we use a simulation model. The hit ratio of private cache memory is a major factor on the linear increase of the performance of a shared memory based multiprocessor system.