• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.2009-2014
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• 2012

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance comparison of TDMA and Lottery bus arbitration policy developed recently due to farious conditions and propose the methods of performance improvement.

• Journal of Korean Society for Geospatial Information Science
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• v.3 no.2 s.6
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• pp.199-211
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• 1995

Bus, Which is together with subway the main part of public transportation modes in the city, is reviewed for the development of an optimal feeder-bus service area. Based on the IDRISI of GIS package, and taking into account of the convenience of downtown-oriented public transportation users at peak time, a model for the development of feeder-bus service area and a solution and introduced. Major result in this study is as follows: Development is given to a model that is designed to overcome the shortage of the existing models, which has limits in simulating the real situation; Variables were used in combination so that bus and subway route, station spacing, and operating frequency can be determined simultaneously, which enables to elucidate the mutual relationship and the structure in public transportation system. A model for feeder-bus area development is also given applied to determination and opening of subway and urban express bus route and new transportation systems. The model developed in this paper is useful in the case of extension and opening of subway and urban express bus route and new transportation Systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.8
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• pp.1879-1884
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• 2013

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. In this paper, we draw the performance analysis of Fixed Priority, Round Robin, TDMA and Lottery bus arbitration policies due to the data traffic concentration and propose the methods of performance improvement.

• Journal of Digital Convergence
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• v.15 no.10
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• pp.63-81
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• 2017

Objectives of this study are to analyze the previous research perfomed in the Bus Information System (BIS) area and to suggest future research directions. This is a very meaningful and important work. To accomplish this, this study (1) summarizes the concepts of BIS, (2) establishes a research framework to be used to analyze the previous studies in the area, and (3) identifies and suggest trends and future directions of the BIS research. This study has identified total of 68 article (22 foreign and 46 domestic) using 'Google Scholoar' search engine. Major research results include (1) since non-empirical research is dominant, more explanatory empirical research is needed in the future, (2) research that provides consistent and comprehensive measures for BIS related constructs (e.g., BIS quality) is needed, and (3) impacts on the stakeholders of BIS not reflected in the current research (e.g., bus drivers, administrative agencies) should be analyzed in the future research.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.122-127
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• 2008

General bus stop is very simple and have some problem to protect the passengers and don't have any proper information messenger for the convenience of bus riding in spite of present initiative bus information system. However, this paper have introduced new conceptual modular-smart station avaliable to both public bus and bimodal tram. It can secure the passenger's safety from other danger attributes like running car or unexpected natural disaster and supply the passengers the variable information from display which is connected to the control center. Therefore, modular-smart station is both shelter and information messenger for passenger's safey and convenience.

• Journal of Korean Society of Transportation
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• v.28 no.1
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• pp.135-142
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• 2010

The convenient techniques for predicting the bus arrival time have used the data obtained from the buses belong to the same company only. Consequently, the conventional techniques have often failed to predict the bus arrival time at the downstream bus stops due to the lack of the data during congestion time period. The primary objective of this study is to overcome the weakness of the conventional techniques. The estimation model developed based on the data obtained from Bus Information System(BIS) and Bus management System(BMS). The proposed model predicts the bus arrival time at bus stops by using the data of all buses travelling same roadway section during the same time period. In the tests, the proposed model had a good accuracy of predicting the bus arrival time at the bus stops in terms of statistical measurements (e.g., root mean square error). Overall, the empirical results were very encouraging: the model maintains a prediction job during the morning and evening peak periods and delivers excellent results for the severely congested roadways that are of the most practical interest.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2433-2438
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• 2011

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, bus system performance can be changed definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this study, we proposed the score arbitration method and synthesized it using Hynix 0.18um technology, after design of RTL. Also we analyze the performance compared with general arbitration methods through simulation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.8
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• pp.98-105
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• 2008

FlexRay is a high-speed communications protocol with high flexibility and reliability. It was devised by automotive manufacturers and semiconductor vendors and implemented as on vehicle LAN protocol using x-by-wire systems. FlexRay provides a high speed serial communication, time triggered bus and fault tolerant communication between electronic devices for automotive applications. In this paper, we first design the FlexRay communication controller, bus guardian protocol specification and function parts using SDL (Specification and Description Language). Then, the system is re-designed using Verilog HDL based on the SDL source. The FlexRay system was synthesized using Samsung $0.35{\mu}m$ technology. It is shown that the designed system can operate in the frequency range above 76 MHz. In addition, to show the validity of the designed FlexRay system, the FlexRay system is combined with automobile advance alarm system in vehicle applications. The FlexRay system is implemented using ALTERA Excalibur ARM EPXA4F672C3. It is shown that the implemented system operates successfully.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.76-91
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• 1996

In this paper, we proposed the new medium access control protocol for the virtual token bus netowrk. The network is applied to inter-processor communication network of large capacity digital switching system and digital mobile system with distributed control architecture. in the virtual token bus netowrk, the existing medium access control protocols hav ea switchove rtime overhead when traffic load is light or asymmetric according ot arbitration address of node that has message to send. The proposed protocol optimized average message delay using cyclic bus access chain to exclude switchover time of node that do not have message to send. Therefore it enhanced bus tuilization and average message delay that degrades the performance of real time communication netowrks. It showed that the proposed protocol is more enhacned than virtual token medium access control protocol and virtual token medium access control protocol iwth reservation through performance analysis.