• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.8A
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• pp.644-649
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• 2003

Novel 622Mb/s burst-mode clock and data recovery (CDR) circuits with muxed oscillators are realized for passive optical network (PON) application. The CDR circuits are implemented with 0.35$\mu\textrm{m}$ CMOS process technology. Lock is accomplished on the first data transition and data are sampled in the optimal point. The experimental results show that the proposed CDR circuits recover the incoming 400Mbps-680Mbps burst mode input data without error.

• Journal of the Optical Society of Korea
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• v.12 no.4
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• pp.355-358
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• 2008

In the current GPON market and standard, the line bit rate requirement is changing from 1.25 Gbps to 2.5 Gbps. We fabricate a 2.5 Gbps burst-mode receiver with commercially available blocks and optimize it with an APD bias control. A burst-mode measurement setup is made for the full compliance test with the GPON standard. The device meets the partially defined 2.5 Gbps specs in the current ITU G.984.2 standard, also, supports 1.25 Gbps specs for the coexistence issue in an access network. The full-compliant measurement values can be used as a guideline for fixing "for further study" specs in the current GPON standard at 2.5 Gbps.

• Journal of Advanced Navigation Technology
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• v.13 no.3
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• pp.337-343
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• 2009

In this paper, we proposed a burst mode symbol timing recovery unit that is applicable to the VDL Mode-2 using D8PSK modulation. A method that IIR loop filter is used to minimize symbol timing error is hard to apply to burst mode because its convergence time is long. That is, the fast convergence property is important. In this paper, the proposed method takes one sample which has maximum symbol power after the initial synchronization has been achieved by using preambles. The main principle of operation is that the unit moves one sample clock to advance or retard according to symbol power. We verify that the proposed method is operated well in ${\pm}100$ ppm or greater through the test results between Australia ADS Corp. transmitter and the designed receiver.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.9-15
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• 2009

In this paper, we invented a new structure of fast ATC(Automatic Threshold Control) circuit. Using the structure we made a new burst-mode limiting amplifier with fast ATC function using commercial $0.8{\mu}m$ BiCMOS technology. It's ATC function worked so fast that even the first bit of burst-data could be detected, which confirmed that the new structure was useful for fast ATC. However, in the beginning of a burst, distortions in duty-cycle occurred and increased up to 59% of duty-cycle as amplitude of input signal increased. But we confirmed that after 10 cycles passed, duty-cycles was staying below 52% of duty-cycle for any magnitude of input signal.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.12
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• pp.25-30
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• 2007

In this paper, we proposed a new burst-mode optical transmitter structure which is suitable for high data rate operation such as Gb/s operation. With this structure we made a 1.25Gb/s burst-mode optical transmitter including a digitally controlled APC circuit for EPON systems using commercial 0.8m BiCMOS technology. It well functioned at 1.25Gb/s and showed good eye patterns with 53.3ps jitter, 191ps rise time and 258ps fall time. To characterize the APC function we measured optical output power as increasing external voltage VREF. The optical power is linearlyproportional to VREF at the rate of 0.293mW/V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.21-26
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• 2008

In this paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuits are implemented with 0.35um CMOS process technology. Locking dynamics is accomplished with instantaneous feature and data are sampled at an optimal timing. This is realized by seven different delay configurations, which are generated from precisely-controlled delay buffers. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.2B
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• pp.111-119
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• 2011

As Green-IT has attracted a lot of attention in recent years, many researches have been interested in reducing the energy consumption of network equipments. In this paper, we analyze the energy saving ratio and delay performance according to various traffic patterns and burst assemble algorithms in OBS network with sleeping mode. To do this, we design the traffic generators, which are based on exponential distribution and Pareto distribution, and the router model, which has the time based and length based burst assemble algorithms by using OPNET modeler. Through OPNET simulator, we evaluate the energy saving performance in terms of the sleeping time, the number of transitions and packet delay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.98-104
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• 2006

The conventional burst-mode APC(Automatic Power Control) circuit had an effective structure that was suitable for a low power consumption and a monolithic chip. However, as data rate was increased, it caused errors due to the effect of the zero density. In this paper, we invented a new structured peak-comparator which could compensate the unbalance of the injected currents using double gated MOS and MOS diode. And we proposed a new burst-mode APC adopting it. The new peak-comparator in the proposed APC was very robust to zero density variations maintaining the correct decision point of the current comparison at high data rate. It was also suitable for a low power consumption and a monolithic chip due to lack of large capacitors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.67-74
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• 2004

As data rate was increased, the conventional burst-mode automatic power control circuit caused errors due to the effort of the mark density variation. To solve this problem we invented a new structured peak-comparator which could eliminate the effect of the mark density variation even in high date rate, and revised the conventional one using it. We proposed a burst-mode automatic power control circuit robust to mark density variations. We found that the peak-comparator in the proposed automatic power control circuit was very robust to mark density variations because it affected very little by the mark density variation in high date rate and in the wide variation range of the reference current and the difference current.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1609-1618
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• 2015

DC microgrids are considered as prospective systems because of their easy connection of distributed energy resources (DERs) and electric vehicles (EVs), reduction of conversion loss between dc output sources and loads, lack of reactive power issues, etc. These features make them very suitable for future industrial and commercial buildings' power systems. In addition, the bipolar-type dc system structure is more popular, because it provides two voltage levels for different power converters and loads. To keep voltage balanced in such a dc system, a bidirectional dual buck-boost voltage balancer with direct coupling is introduced based on P-cell and N-cell concepts. This results in greatly enhanced system reliability thanks to no shoot-through problems and lower switching losses with the help of power MOSFETs. In order to increase system efficiency and reliability, a novel burst-mode control strategy is proposed for the dual buck-boost voltage balancer. The basic operating principle, the current relations, and a small-signal model of the voltage balancer are analyzed under the burst-mode control scheme in detail. Finally, simulation experiments are performed and a laboratory unit with a 5kW unbalanced ability is constructed to verify the viability of the bidirectional dual buck-boost voltage balancer under the proposed burst-mode control scheme in low-voltage bipolar-type dc microgrids.