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Burst-mode Clock and Data Recovery Circuit in Passive Optical Network Implemented with a Phase-locked Loop  

Lee, Sung-Chul (Department of Electronic Engineering, Hallym University)
Moon, Sung-Young (Department of Electronic Engineering, Hallym University)
Moon, Gyu (Department of Electronic Engineering, Hallym University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.4, 2008 , pp. 21-26 More about this Journal
Abstract
In this paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuits are implemented with 0.35um CMOS process technology. Locking dynamics is accomplished with instantaneous feature and data are sampled at an optimal timing. This is realized by seven different delay configurations, which are generated from precisely-controlled delay buffers. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.
Keywords
Phase-Locked Loop(PLL); Clock and Data Recovery(CDR); Passive Optical Network(PON); Burst-mode;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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