• 전자공학회논문지C
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• 제34C권8호
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• pp.49-63
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• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• 전자공학회논문지B
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• 제32B권11호
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• pp.1434-1444
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• 1995

Current test has recently been known to be a promising testing method in CMOS VLSI because conventional voltage test can not make sure of the complete detection of bridging, gate-oxide shorts, stuck-open faults and etc. This paper presents a new BIC(built-in current sensor) for the internal current test in CMOS logic circuit. A single phase clock is used in the BIC to reduce the control circuitry of it and to perform a self- testing for a faulty current. The BIC is designed to detect the faulty current at the end of the clock period, so that it can test the CUT(circuit under test) with much longer critical propagation delay time and larger area than conventional BICs. The circuit is composed of 18 devices and verified by using the SPICE simulator.

• 전기학회논문지
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• 제56권2호
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• pp.361-366
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• 2007

In the distribution networks, it is necessary to develop small and light voltage and current sensor for compact and digitalized switchgears. For this purpose, some researches have been continuing till now, CT(current transformer) and VT(voltage transformer) are one of that research. But conventional CT and VT have some problems, that is, have big size and saturation characteristics because of used to iron core. In this paper, CS(current sensor) and VS(voltage sensor), have some merits measuring of current and voltage magnitude as a alternated conventional equipment, were studied. So, this paper shows the process CS and VS design method, equivalent circuit and output result, respectively. As a result of this test, proposed CS and VS have linearity for the output, no saturation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 A
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• pp.271-274
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• 2003

This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

• 한국멀티미디어학회논문지
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• 제10권10호
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• pp.1260-1270
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• 2007

테스트 기술자들에게 아날로그 회로(또는 혼합신호 회로)의 테스트와 진단은 여전히 어려운 문제여서 이를 해결할 수 있는 효과적인 테스트 방법이 크게 요구된다. 본 논문에서는 time slot specification(TSS) 기반의 내장 전류감지기(Built-in Current Sensor)를 이용한 새로운 아날로그 회로의 테스트 기법을 제안한다. 또한 TSS에 기반 하여 고장 위치를 찾아내고 고장의 종류를 구별해 내는 방법을 제시한다. TSS 기법과 함께 제안하는 내장 전류감지기는 높은 고장 용이도와 높은 고장 검출을 그리고 아날로그 회로내 강고장과 약고장에 대한 높은 진단율을 갖는다. 제안하는 방법에서는 주출력과 전원단자등을 테스트 포인트로 사용하고 전류감지기를 자동 테스트 장치(Automatic Test Equipment)에 구성하므로써 테스트 포인트 선택과정의 복잡도를 줄일 수 있다. 내장 전류 감지기의 디지털 출력은 아날로그 IC 테스트를 위한 내장 디지털 테스트 모듈과 쉽게 연결된다.

• 전기전자학회논문지
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• 제9권1호
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• pp.57-64
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• 2005

본 논문에서는 전류 테스팅을 이용하여 CMOS 집적회로에 존재하는 결함을 검출하는 내장형 전류 감지회로를 설계하였다. 이 회로는 일반적인 CMOS 공정으로 구현하였으며 결함전류와 기준전류를 전압으로 변환시켜 시험대상 회로의 결함을 고속으로 검출하며, 미세공정에도 적용가능한 회로이다 제안한 전류 감지회로는 전류원 내장으로 인한 추가적인 전력소모를 문제를 해결하였다. 제안한 회로의 정당성 및 효율성은 HSPICE를 이용한 시뮬레이션으로 그 타당성을 입증하였다. 제안한 전류 감지회로가 칩의 전체 면적에서 차지하는 면적소모는 시험대상회로에서 약 9.2%로, 내장형 전류 감지회로에 의한 면적소모는 무시할 만 하다. 제안한 회로는 Hynix O.35um 2-poly 4-metal N-Well 표준 CMOS 공정으로 제작하였다.

• 대한기계학회논문집
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• 제19권9호
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• pp.2082-2088
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• 1995

In this paper, we designed and fabricated the magnetic bearings and built-in type cylindrical capacitive transducers for improving the vibration characteristics of rotating shaft. The eddy current and magnetic field from the electromagnet of the bearing don't affect the measuring signal of the capacitive type transducers so that it is possible to locate the capacitive sensor plates around the magnetic bearing poles and can improve the spillover problem which is induced by the noncollocation of the sensors and actuators. According to the sensitivity calibration schemes using a X-Y table, the cylindrical capacitive transducers have a good linearities in the .+-.70.mu.m range from the geometric center of the sensor plates. The measured results also show high displacement sensitivities of the sensors. According to the performance test of the magnetic bearing which is controlled by the analog PD controllers, we found that the built-in capacitive transducer system successfully measures the journal displacement in the magnetic field and therefore the magnetic bearing system supports the rotating shaft up to 12,000 rpm.

• 한국음향학회지
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• 제18권3호
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• pp.43-48
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• 1999

IDDQ 테스트는 CMOS 소자로 구성된 회로에서 기능 테스트로는 검출할 수 없는 결함을 찾아내어 회로의 신뢰성을 높여주는 전류테스트 방식이다. 본 논문에서는 IDDQ 테스트를 테스트 대상 칩 내에서 수행할 수 있는 내장전류감지(Built-In Current Sensor : BICS)회로를 설계하였다. 이 회로는 메모리의 IDDQ 테스트를 수행할 수 있도록 설계되었으며, 적은 트랜지스터를 사용하여 빠른 시간 내에 테스트를 수행할 수 있도록 구현하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.1254-1257
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• 2004

This paper presents a built-in current sensor(BICS) that can detect defects in CMOS integrated circuits through current testing technique - Iddq test. Current test has recently been known to a complementary testing method because traditional voltage test cannot cover all kinds of bridging defects. So BICS is widely used for current testing. but there are some critical issues - a performance degradation, low speed test, area overhead, etc. The proposed BICS has a two operating mode- normal mode and test mode. Those methods minimize the performance degradation in normal mode. We also used a current-mode differential amplifier that has a input as a current, so we can realize higher speed current testing. Furthermore, only using 10 MOSFETS and 3 inverters, area overhead can be reduced by 6.9%. The circuit is verified by HSPICE simulation with 0.25 urn CMOS process parameter.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.431-438
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• 2005

In this paper, we propose the built-in current testing circuit for improving reliability As the integrated CMOS circuits in a chip are increased, the testability on design and fabrication should be considered to reduce the cost of testing and to guarantee the reliability In addition, the high degree of integration makes more failures which are different from conventional static failures and introduced by the short between transistor nodes and the bridging fault. The proposed built-in current testing method is useful for detecting not only these failures but also low current level failures and faster than conventional method. In normal mode, the detecting circuit is turned off to eliminate the degradation of CUT(Circuits Under Testing). The differential input stage in detecting circuit prevents the degradation of CUT in test mode. It is expected that this circuit improves the quality of semiconductor products, the reliability and the testability.