• Journal of Power Electronics
• /
• v.15 no.6
• /
• pp.1609-1618
• /
• 2015

DC microgrids are considered as prospective systems because of their easy connection of distributed energy resources (DERs) and electric vehicles (EVs), reduction of conversion loss between dc output sources and loads, lack of reactive power issues, etc. These features make them very suitable for future industrial and commercial buildings' power systems. In addition, the bipolar-type dc system structure is more popular, because it provides two voltage levels for different power converters and loads. To keep voltage balanced in such a dc system, a bidirectional dual buck-boost voltage balancer with direct coupling is introduced based on P-cell and N-cell concepts. This results in greatly enhanced system reliability thanks to no shoot-through problems and lower switching losses with the help of power MOSFETs. In order to increase system efficiency and reliability, a novel burst-mode control strategy is proposed for the dual buck-boost voltage balancer. The basic operating principle, the current relations, and a small-signal model of the voltage balancer are analyzed under the burst-mode control scheme in detail. Finally, simulation experiments are performed and a laboratory unit with a 5kW unbalanced ability is constructed to verify the viability of the bidirectional dual buck-boost voltage balancer under the proposed burst-mode control scheme in low-voltage bipolar-type dc microgrids.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.12 no.6
• /
• pp.465-471
• /
• 2007

The system efficiency of the proposed Buck-Boost AC-DC converter is increased by soft switching method. The converter includes to merit of power factor correction (PFC) from sinusoidal control of input current. The switching behavior of control switches operates with soft switching by partial resonance, and then the proposed converter has high system efficiency with decrement of switching power loss. The input current waveform in proposed converter is got to be a sinusoidal form of discontinuous quasi-pulse row in proportion to magnitude of AC input voltage under the constant duty cycle switching. Therefore, the input power factor is nearly unity. The output voltage of the converter is regulated by PWM control technique. The discontinuous mode action of current flowing into inductor makes to simplify control method and control components. The proposed PFC Buck-Boost converter is analyzed to compare with the conventional PFC Buck-Boost converter. Some computer simulative results and experimental results confirm to the validity of the analytical results.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.22 no.4
• /
• pp.360-368
• /
• 2017

This paper proposes the 80-kW high-efficiency bidirectional hybrid SiC boost/buck converter using droop control for DC nano-grid. The proposed converter consists of four 20-kW modules to achieve fault tolerance, ease of thermal management, and reduced component stress. Each module is constructed as a cascaded structure of the two basic bi-directional converters, namely, interleaved boost and buck converters. A six-pack hybrid SiC intelligent power module (IPM) suitable for the proposed cascaded structure is adopted for high-efficiency and compactness. The proposed converter with hybrid switching method reduces the switching loss by minimizing switching of insulated gate bipolar transistor (IGBT). Each module control achieves smooth transfer from buck to boost operation and vice versa, since current controller switchover is not necessary. Furthermore, the proposed parallel control using DC droop with secondary control, enhances the current sharing accuracy while well regulating the DC bus voltage. A 20-kW prototype of the proposed converter has been developed and verified with experiments and indicates a 99.3% maximum efficiency and 98.8% rated efficiency.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.35 no.11B
• /
• pp.1667-1675
• /
• 2010

This paper presents a high efficiency DC-DC buck converter for mobile device. The circuit employes simplified compensation circuit for its portability and for high efficiency at stand-by mode. This device operates at PFM mode when it enters stand-by mode(light load). In order to place the compensation circuit on chip, the capacitor multiplier method is employed, such that it can minimize the compensation block size of the error amplifier down to 30%. The measurement results show that the buck converter provides a peak efficiency of 93% on PWM mode, and 92.3% on PFM mode. The converter has been fabricated with a $0.35{\mu}m$ CMOS technology. The input voltage of the buck converter ranges from 2.5V to 3.3V and it generates the output of 3.3V.

• Journal of IKEEE
• /
• v.15 no.4
• /
• pp.330-338
• /
• 2011

In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).

• Journal of IKEEE
• /
• v.17 no.1
• /
• pp.77-82
• /
• 2013

In this paper, dc-dc buck converter controled by the peak current-mode pulse-width-modulation (PWM) presented. Based on the small-signal model, we propose the novel methods of the power stage and the systematic stability designs. To improve the reliability and performance, over-temperature and over-current protection circuits have been designed in the dc-dc converter systems. To prevent electrostatic An electrostatic discharge (ESD) protection circuit is proposed. The proposed dc-dc converter circuit exhibits low triggering voltage by using the gate-substrate biasing techniques. Throughout the circuit simulation, it confirms that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS (8.2V). The circuit simulation is performed by Mathlab and HSPICE programs utilizing the 0.35um BCD (Bipolar-CMOS-DMOS) process parameters.

• Journal of Power Electronics
• /
• v.19 no.4
• /
• pp.846-857
• /
• 2019

Voltage step-down converters are very popular in distributed power systems, voltage regular modules, electric vehicles, etc. However, a high step-down voltage ratio is required in many applications to prevent the traditional buck converter from operating at extreme duty cycles. In this paper, a series capacitor interleaved buck converter with a soft switching technique is proposed. The DC voltage ratio of the proposed converter is half that of the traditional buck converter and the voltage stress across the one main switch and the diodes is reduced. Moreover, by paralleling the series connected auxiliary switch and the auxiliary inductor with the main inductor, zero voltage transition (ZVT) of the main switches can be obtained without increasing the voltage or current stress of the main power switches. In addition, zero current turned-on and zero current switching (ZCS) of the auxiliary switches can be achieved. Furthermore, owing to the presence of the auxiliary inductor, the turned-off rate of the output diodes can be limited and the reverse-recovery switching losses of the diodes can be reduced. Thus, the efficiency of the proposed converter can be improved. The DC voltage gain ratio, soft switching conditions and a design guideline for the critical parameters are given in this paper. A loss analysis of the proposed converter is shown to demonstrate its advantages over traditional converter topologies. Finally, experimental results obtained from a 100V/10V prototype are presented to verify the analysis of the proposed converter.

• Journal of Convergence for Information Technology
• /
• v.11 no.3
• /
• pp.14-19
• /
• 2021

In this paper, a method of constructing an inverter circuit that can generate negative voltage required to operate an IT device in a stable using an inexpensive buck device is presented. To do this, the problem of constructing the inverter circuit using the existing buck device was examined, the principle that could prevent this problem was analyzed, and a circuit that could solve this problem was presented. In order to prove the effectiveness of the proposed method, the experimental circuit was constructed and the experiment was conducted. Compared to the operation of the inverter circuit by the existing overcurrent prevention circuit, it was confirmed that the stable operation was performed without an overcurrent phenomenon. Accordingly, it is expected that the performance of the circuit can be greatly improved while a number of peripheral devices for configuring the devices for processing various analog signals used in IT devices as a single power supply can be omitted.

• Journal of Power Electronics
• /
• v.5 no.2
• /
• pp.104-108
• /
• 2005

This paper presents the performance improvement of voltage-mode controlled interleaved synchronous buck converters. This is a voltage-mode controlled scheme, where the controllers do not need an external saw-tooth generator for PWM generation and the loop design is easier. The controller implementation requires only a single error amplifier and gives almost current mode control performance. The control scheme uses voltage feedback with two loops similar to current mode control: one for the slow outer loop and the other for the faster inner PWM control loop. To improve the performance of the converter system a coupled inductor is used. This coupled inductor reduces the magnetic size and also improves the converter's transient performance without increasing the steady-state current ripple. The effectiveness of the proposed control scheme is demonstrated through PSIM simulations.

• 제어로봇시스템학회:학술대회논문집
• /
• 2004.08a
• /
• pp.2051-2054
• /
• 2004

This paper proposes a more accurate task level energy measurement technique for high speed microprocessors. The technique is based on the relationship of the amount of current consumed by the microprocessor and the pulse width of the power supply controller chip, employed in the synchronous buck DC-DC converter in the microprocessor's power supply. The accuracy of the measurement is accomplished by measuring variation in pulse width in each power supply cycle. The major advantage of this technique is that its accuracy does not depend on the operating frequency of the microprocessor. To prove the proposed technique, we implemented the measurement unit of the microprocessor energy meter using an FPGA chip operating at 50 MHz. Both static and dynamic load measurement are tested in order to obtain some behaviours. Moreover, various commercially available mainboards which employ synchronous buck regulators at 200 KHz switching frequency, were measured. The results agree with previous works with better accuracy at higher operating frequency.