• Journal of Power Electronics
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• v.19 no.1
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• pp.278-287
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• 2019

In this study, a zero-crossing spike current issue in a totem-pole bridgeless power factor correction (PFC) converter is comprehensively investigated for the first time. Spike current occurs when input voltage crosses zero, becomes a noise source, and causes severe common mode emission issues. A generation mechanism for electromagnetic interference (EMI) is presented to investigate the EMI problem caused by zero-crossing issue, and a noise spectrum due to this issue is predicted by a theoretical analysis based on the Fourier coefficient of an approximate spike current waveform. Furthermore, a noise reduction method is proposed and then improved to reduce the spike current. Experimental measurements are implemented on a GaN-based totem-pole bridgeless PFC converter, and the spike current can be effectively suppressed through the proposed method. Furthermore, the noise spectrums measured without and with the reduced zero-crossing spike current are compared. Experimental results validate the analysis of the noise spectrum caused by the zero-crossing spike current issue.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.3
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• pp.214-222
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• 2015

The superiority of gallium nitride FET (GaN FET) over silicon MOSFET is examined in this paper. One of the outstanding features of GaN FET is low reverse-recovery charge, which enables continuous conduction mode operation of totem-pole bridgeless boost power factor correction (PFC) circuit. Among many bridgeless topologies, totem-pole bridgeless shows high efficiency and low conducted electromagnetic interference performance, with low cost and simple control scheme. The operation principle, control scheme, and circuit implementation of the proposed topology are provided. The converter is driven in two-module interleaved topology to operate at a power level of 5.5 kW, whereas phase-shedding control is adopted for light load efficiency improvement. Negative bias circuit is used in gate drivers to avoid the shoot-through induced by high speed switching. The superiority of GaN FET is verified by constructing a 5.5 kW prototype of two-module interleaved totem-pole bridgeless boost PFC converter. The experiment results show the highest efficiency of 98.7% at 1.6 kW load and an efficiency of 97.7% at the rated load.

• Journal of Power Electronics
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• v.13 no.1
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• pp.40-50
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• 2013

In this paper, a new zero-voltage-switching, high power-factor, bridgeless rectifier is introduced. In this topology, an auxiliary circuit provides soft switching for all of the power semiconductor devices. Thus the switching losses are reduced and the highest efficiency can be achieved. The proposed converter has been analyzed and a design procedure has been introduced. The control circuit for the converter has also been developed. Based on the given approach, a 250 W, 400 Vdc prototype converters has been designed at 100 kHz for universal input voltage (90-264 Vrms) applications. A maximum efficiency of 94.6% and a power factor correction over 0.99 has been achieved. The simulation and experimental results confirm the design procedure and highlight the advantages of the proposed topology.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.145-146
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• 2016

일반적인 boost PFC 컨버터는 한 개의 스위칭 소자를 사용하고 구조가 간단하지만 높은 도통손실과 스위칭 손실 때문에 낮은 효율을 갖는다. bridgeless boost PFC 컨버터는 일반적인 boost PFC 에 비해 낮은 손실을 갖는 이점이 있다. 또한 컨버터의 동작 모드 중 CRM 방식은 낮은 스위칭 손실을 갖는 이 점이 있다. 본 논문에서는 이러한 CRM 모드로 동작하는 bridgeless boost PFC 컨버터를 해석하는 경우 기존의 방법으로 해석하여 구현하면 주파수가 커지는 영역에서 오차가 커지게 된다. 따라서 본 논문에서는 반도체 스위치의 기생 커패시터를 추가하여 해석하는 것을 제안하였다.

• Journal of Power Electronics
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• v.15 no.2
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• pp.356-365
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• 2015

This paper presents a new single phase front-end ac-dc bridgeless power factor correction (PFC) rectifier topology. The proposed converter achieves a high efficiency over a wide range of input and output voltages, a high power factor, low line current harmonics and both step up and step down voltage conversions. This topology is based on a non-inverting buck-boost (Zeta) converter. In this approach, the input diode bridge is removed and a maximum of one diode conducts in a complete switching period. This reduces the conduction losses and the thermal stresses on the switches when compare to existing PFC topologies. Inherent power factor correction is achieved by operating the converter in the discontinuous conduction mode (DCM) which leads to a simplified control circuit. The characteristics of the proposed design, principles of operation, steady state operation analysis, and control structure are described in this paper. An experimental prototype has been built to demonstrate the feasibility of the new converter. Simulation and experimental results are provided to verify the improved power quality at the AC mains and the lower conduction losses of the converter.

• Journal of Power Electronics
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• v.18 no.2
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• pp.323-331
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• 2018

Buck power factor correction (PFC) converters, compared with conventional boost PFC converters, exhibit high efficiency performance in the entire range of universal line voltage. This feature has gotten more attention for eliminating the zero crossing dead angle of buck PFC rectifiers. Furthermore, bridgeless structures for the reduction of conduction losses have been proposed. The aim of this paper is to introduce a single-phase buck rectifier that simultaneously has unity power factor (PF) and bridgeless structure while operating in the continuous conduction mode (CCM). For this purpose, two auxiliary flyback converters without any active switches are applied to a bridgeless buck rectifier to eliminate the zero crossing dead angle and achieve unity power factor, low total harmonic distortion (THD) and high efficiency. The operation and design considerations of the proposed rectifier are verified on a 150W, 48V prototype using a conventional peak-current-mode control. The measurement results show that the proposed rectifier has nearly unity power factor, THD less than 7% and high efficiency.

• Proceedings of the KIPE Conference
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• 2010.11a
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• pp.26-27
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• 2010

기존의 역률 보상 회로(PFC 회로)는 저전압 입력 시에 정류 다이오드의 도통손실 증가로 인해 효율 상승에 제약을 받는다. Bridgeless PFC 컨버터는 입력 측의 정류 다이오드 없이 능동 스위치가 정류 동작을 수행하도록 하여 더 높은 효율을 얻을 수 있다. 본 논문에서는 고효율을 위한 새로운 절연형 bridgeless PFC 컨버터를 제안한다. 제안한 회로는 입력단의 정류 다이오드를 제거함으로써 도통 손실을 줄여 효율 향상을 꾀하였다. 또한 변압기를 사용하여 입출력 전압 이득 설계를 자유롭게 하였으며, 2차 DC/DC 컨버터 설계 시 절연이 필요하지 않도록 하였다. 제안한 회로의 성능을 65W급 프로토타입 컨버터의 실험을 통해 검증하였다.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.704-708
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• 2004

Recently, many nation have released standard such as IEC 61000-3-2 and IEEE 59, which impose a limit on the harmonic current drawn by equipment connected to AC line in order to prevent the distortion of an AC Line. Therefore, Plasma Display Panel (PDP) which is highlightened in digital display device also has the Power Factor Correction (PFC) circuit to meet the harmonic requirements. In PDP power module, the conventional boost converter is usually used for the PFC circuit. However, it comes serious thermal problem on it's bridge diode due to heat of PDP, and therefore the system stability is not guaranteed. In this paper, the bridgeless boost converter, which is used for PFC circuit of the PDP power module, is designed and verified the possibility of the application in a practical product in a view of efficiency, component count, temperature and etc.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.12
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• pp.2000-2007
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• 2016

Generally, in order to implement the CRM(Critical Conduction Mode), the analog controller is used rather than a digital controller because the control is simple and uses less power. However, according to the semiconductor technology development and various user needs, digital control system based on a DSP is on the rise. Therefore, in this paper, the CRM bridgeless PFC converter based on a digital control is proposed. It is necessary to detect the inductor current when it reaches zero and peak value, for calculating the on time and off time by using the current information. However, in this paper, the on-time and off-time are calculated by using the proposed algorithm without any current information. If the switching-times are calculated through the steady-state analysis of the converter, they do not reflect transient status such as starting-up. Therefore, the calculated frequency is out of range, and the transient current is generated. In order to solve these problems, limitation method of the on-time and off-time is used, and the limitation values are varied according to the voltage reference. In addition, in steady state, depending on the switching frequency, the inductance is varied because of the resonance between the inductor and the parasitic capacitance of the switching elements. In order to solve the problem, inductance are measured depending on the switching frequency. The measured inductance are used to calculate the switching time for preventing the transient current. Simulation and experimental results are presented to verify the proposed method.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.293-301
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• 2011

This paper proposes a bridgeless half-bridge AC-DC converter with high-efficiency. The proposed converter integrates the bridgeless power factor correction (PFC) circuit with the asymmetrical pulse-width modulated (APWM) half-bridge DC-DC converter. It provides the isolated DC output voltage from the AC line voltage without using any full-bridge diode rectifier. Conduction losses are lowered with a simple circuit structure. Switching losses are also reduced by achieving zero-voltage switching (ZVS) of the power switches. By using series-connected two transformers, the proposed converter provides a low-profile and high power density for AC-DC converters. The performance of the proposed converter is verified from a 250 W (48 V / 5.2 A) experimental prototype circuit at $90 \;V_{rms}$ line voltage.