Fig. 1. Proposed bridgeless unity power factor buck rectifier.
Fig. 2. Operation of the positive and negative half-line cycles. (a)Positive half-line cycle. (b) Negative half-line cycle.
Fig. 3. Theoretical key waveforms.
Fig. 4. Equivalent circuits of the three modes during the positivehalf-line cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3.
Fig. 5. An equivalent circuit of the second mode.
Fig. 6. Schematic of the implemented circuit.
Fig. 7. Measured line waveforms at Po=150 W. (a) Line current and voltage waveforms (time: 5 ms/div). (b) Measured odd harmoniccomponents of the line current with the Class D requirements of JIS C 6100-3-2.
Fig. 8. Measured waveforms at Po=150 W. (a) Low frequency voltages (10 V/div; time: 5 ms/div). (b) Switching currents at the peak ofthe line voltage (8 A/div; time: 10 μs/div). (c) Switching voltages at the peak of the line voltage (time: 10 μs/div).
Fig. 9. Measured ef?ciency, PF and THD compared with outputpower.
TABLE I COMPARISON OF THE PROPOSED RECTIFIER AND THE TOPOLOGIES IN [21]-[25]
TABLE II COMPARISON OF THE PF, THD AND EFFICIENCY OF THE PROPOSED RECTIFIER AND STATE-OF-THE-ART BUCK RECTIFIERS FOR 110 VAC LINE VOLTAGE
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