• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.46-49
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• 1994

In this paper we investigate the characteristics of switching and memory traps in sealed MONOS nonvolatile memory devices with different nitride thicknesses. We have demonttrated flatband voltage shift of 1V with 5V programming voltage. By fitting the experimental observations with theoretical calculations, trap density and capture cross section of memory trap at the nitride-blocking oxide interface are estimated to be 1.0${\times}$10$\^$13/ cm$\^$-2/ and 8.0${\times}$10$\^$14/ cm$\^$-2/

• 한국전기전자재료학회논문지
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• 제22권1호
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• pp.7-11
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• 2009

In this study, p-channel silicon-oxide-nitride-oxide-silicon(SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are 2.0 nm for the tunnel oxide, 1.4 nm for the nitride layer, and 4.9 nm for the blocking oxide. The fabricated SONOS transistors show low programming voltage and fast erase speed. However, the retention and endurance of the devices show poor characteristics.

• 진공이야기
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• 제2권2호
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• pp.12-16
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• 2015

Organic photovoltaics (OPVs) have attracted significant interest in an interdisciplinary research field for the decades as a next-generation photovoltaic device due to their unique advantages. One of requirements for OPVs having high power conversion efficiency is the favorable energy level alignment between the electrode/organic and organic/organic interfaces to manage the exciton dissociation and improve the charge transport. In this review, strategies to enhance the OPV performance by controlling the energy level alignment are discussed. The insertion of an exciton blocking layer leads to the efficient dissociation of photogenerated excitons at the donor/acceptor interface enhancing the short-circuit current density. The choice of a donor having a high ionization energy and an acceptor having a low electron affinity increases the open-circuit voltage. The insertion of an appropriate work function modifier which reduces the charge injection barrier removes the S-kink in current density-voltage characteristics of OPVs and improves the fill factor. This review would give a valuable guide to design the efficient OPV structure.

• 대한전기학회논문지:전력기술부문A
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• 제53권8호
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• pp.438-445
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• 2004

This paper presents a new numerical spectral domain algorithm devoted to blocking unsuccessful automatic reclosing onto permanent faults and fault distance calculation. Arc voltage amplitude and fault distance are calculated from the fundamental and third harmonics of the terminal voltages and currents phasors. From the calculated arc voltage amplitude it can be concluded if the fault is transient arcing fault or permanent arcless fault. If the fault is permanent automatic reclosure should be blocked. The algorithm can be applied for adaptive autoreclosure, distance protection, and fault location. The results of algorithm testing through computer simulation and real field record are given.

• Journal of Power Electronics
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• 제9권1호
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• pp.36-42
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• 2009

This paper presents a review of an improved high power-high frequency III-V wide bandgap (WBG) semiconductor device, Gallium Nitride (GaN). The device offers better efficiency and thermal management with higher switching frequency. By having higher blocking voltage, GaN can be used for high voltage applications. In addition, the weight and size of passive components on the printed circuit board can be reduced substantially when operating at high frequency. With proper management of thermal and gate drive design, the GaN power converter is expected to generate higher power density with lower stress compared to its counterparts, Silicon (Si) devices. The main contribution of this work is to provide additional information to young researchers in exploring new approaches based on the device's capability and characteristics in applications using the GaN power converter design.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 하계학술대회 논문집 C
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• pp.1556-1558
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• 2003

IGCT devices is a superior devices for power conversion purpose. The basic structure of the IGCT devices is same as that of GTO thyristor. This makes the blocking voltage higher and controllable on-state current higher. In this paper, we present static and dynamic characteristics of 4.5 kV PT-type IGCT devices as a function of minority carrier lifetime, n-base thickness and n-buffer thickness. We should choose proper structural parameters for good electrical characteristics of GCT devices.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전력기술부문
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• pp.79-81
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• 2003

This paper presents development and testing of a new numerical spectral domain algorithm devoted to blocking unsuccessful automatic reclosing onto permanent faults and the fault distance calculation. The arc voltage amplitude and the fault distance are calculated from the fundamental and third harmonics of the terminal voltages and currents phasors. From the calculated arc voltage amplitude it can be concluded if the fault is transient arcing fault or permanent arcless fault. If the fault is permanent automatic reclosure should be blocked. The algorithm can be applied for adaptive autoreclosure, distance protection, and fault location. The results of algorithm testing through computer simulation are given.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.353-356
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• 2004

This paper discribes the analysis of the I-V characteristics of 4H-SiC DiMOSFET with single epi-layer Silicon Carbide has been around for over a century. However, only in the past two to three decades has its semiconducting properties been sufficently studied and applied, especially for high-power and high frequency devices. We present a numerical simulation-based optimization of DiMOSFET using the general-purpose device simulator MINIMIS-NT. For simulation, a loin thick drift layer with doping concentration of $5{\times}10^{15}/cm^3$ was chosen for 1000V blocking voltage design. The simulation results were used to calculate Baliga's figure of Merit (BFOM) as the criterion structure optimization and comparison.

• The Korean Journal of Physiology and Pharmacology
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• 제21권1호
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• pp.75-82
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• 2017

The effects of acepromazine on human ether-$\grave{a}$-go-go-related gene (hERG) potassium channels were investigated using whole-cell voltage-clamp technique in human embryonic kidney (HEK293) cells transfected with hERG. The hERG currents were recorded with or without acepromazine, and the steady-state and peak tail currents were analyzed for the evaluating the drug effects. Acepromazine inhibited the hERG currents in a concentration-dependent manner with an $IC_{50}$ value of $1.5{\mu}M$ and Hill coefficient of 1.1. Acepromazine blocked hERG currents in a voltage-dependent manner between -40 and +10 mV. Before and after application of acepromazine, the half activation potentials of hERG currents changed to hyperpolarizing direction. Acepromazine blocked both the steady-state hERG currents by depolarizing pulse and the peak tail currents by repolarizing pulse; however, the extent of blocking by acepromazine in the repolarizing pulse was more profound than that in the depolarizing pulse, indicating that acepromazine has a high affinity for the open state of the channels, with a relatively lower affinity for the closed state of hERG channels. A fast application of acepromazine during the tail currents inhibited the open state of hERG channels in a concentration-dependent. The steady-state inactivation of hERG currents shifted to the hyperpolarized direction by acepromazine. These results suggest that acepromazine inhibits the hERG channels probably by an open- and inactivated-channel blocking mechanism. Regarding to the fact that the hERG channels are the potential target of drug-induced long QT syndrome, our results suggest that acepromazine can possibly induce a cardiac arrhythmia through the inhibition of hERG channels.

• 대한전자공학회논문지SD
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• 제46권5호
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• pp.9-14
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• 2009

표준 CMOS 공정을 이용한 CMOS 게이트 산화막 안티퓨즈의 새로운 OTP 단위 비트 구조를 제안하였다. 제안된 OTP 단위 비트는 NMOS 게이트 산화막 안티퓨즈를 포함한 3개의 트랜지스터와 인버터 타입 자체 센스 엠프를 포함하고 있다. 그럼에도 불구하고, 레이아웃 면적은 기존 구조와 비슷한 $22{\mu}m^2$이다. 또한, 제안된 OTT 단위 비트는 구조적 특징상 고전압 차단스위치 트랜지스터와 저항과 같은 고전압 차단 요소를 사용하지 않기 때문에, 프로그램 시간은 기존 구조보다 개선된 3.6msec이다. 그리고 제안된 OTP 단위 비트를 포함하는 OTP array는 센스 엠프가 단위 비트마다 집적되어 있기 때문에 기존 OTP array에서 사용된 센스 엠프와 바이어스 생성 회로가 필요 없다.