• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.2
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• pp.347-355
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• 2018

Ransomware uses symmetric-key algorithm such as a block cipher to encrypt users' files illegally. If we find the traces of a block cipher algorithm in a certain program in advance, the ransomware will be detected in increased rate. The inclusion of a block cipher can consider the encryption function will be enabled potentially. This paper proposes a way to determine whether a particular program contains a block cipher. We have studied the implementation characteristics of various block ciphers, as well as the AES used by ransomware. Based on those characteristics, we are able to find what kind of block ciphers have been contained in a particular program. The methods proposed in this paper will be able to detect ransomware with high probability by complementing the previous detection methods.

• The KIPS Transactions:PartC
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• v.13C no.7 s.110
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• pp.843-850
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• 2006

This is devoted to first, to propose a hash chain algorithm that generates more secure key than conventional encryption method. Secondly, we proposes encryption method that is more secure than conventional system using a encryption method that encrypts each block with each key generated by a hash chain algorithm. Thirdly, After identifying the user via wired and wireless network using a user authentication method. We propose a divided session key method so that Although a client key is disclosed, Attackers cannot catch a complete key and method to safely transfer the key using a divided key method. We make an experiment using various size of digital contents files for performance analysis after performing the design and implementation of system. Proposed system can distribute key securely than conventional system and encrypt data to prevent attacker from decrypting complete data although key may be disclosed. The encryption and decryption time that client system takes to replay video data fie is analogous to the conventional method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1993-1999
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• 2011

This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• Journal of IKEEE
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• v.22 no.2
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• pp.233-241
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• 2018

This paper describes a lightweight implementation of a cryptographic processor supporting GCM (Galois/Counter Mode) authenticated encryption (AE) that is based on the two block cipher algorithms of ARIA and AES. It also provides five modes of operation (ECB, CBC, OFB, CFB, CTR) for confidentiality as well as the key lengths of 128-bit and 256-bit. The ARIA and AES are integrated into a single hardware structure, which is based on their algorithm characteristics, and a $128{\times}12-b$ partially parallel GF (Galois field) multiplier is adopted to efficiently perform concurrent processing of CTR encryption and GHASH operation to achieve overall performance optimization. The hardware operation of the ARIA/AES-GCM AE processor was verified by FPGA implementation, and it occupied 60,800 gate equivalents (GEs) with a 180 nm CMOS cell library. The estimated throughput with the maximum clock frequency of 95 MHz are 1,105 Mbps and 810 Mbps in AES mode, 935 Mbps and 715 Mbps in ARIA mode, and 138~184 Mbps in GCM AE mode according to the key length.

• Journal of Advanced Navigation Technology
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• v.19 no.1
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• pp.48-52
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• 2015

In this paper, we propose a differential fault analysis on SSB having same structure in encryption and decryption proposed in 2011. The target algorithm was designed using advanced encryption standard and has advantage about hardware implementations. The differential fault analysis is one of side channel attacks, combination of the fault injection attacks with the differential cryptanalysis. Because SSB is suitable for hardware, it must be secure for the differential fault analysis. However, using proposed differential fault attack in this paper, we can recover the 128 bit secret key of SSB through only one random byte fault injection and an exhausted search of $2^8$. This is the first cryptanalytic result on SSB having same structure in encryption and decryption.

• Journal of Information Processing Systems
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• v.8 no.1
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• pp.159-174
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• 2012

This paper presents a study on a high-performance design for a block cipher algorithm implemented on modern many-core graphics processing units (GPUs). The recent emergence of VLSI technology makes it feasible to fabricate multiple processing cores on a single chip and enables general-purpose computation on a GPU (GPGPU). The GPU strategy offers significant performance improvements for all-purpose computation and can be used to support a broad variety of applications, including cryptography. We have proposed an efficient implementation of the encryption/decryption operations of a block cipher algorithm, SEED, on off-the-shelf NVIDIA many-core graphics processors. In a thorough experiment, we achieved high performance that is capable of supporting a high network speed of up to 9.5 Gbps on an NVIDIA GTX285 system (which has 240 processing cores). Our implementation provides up to 4.75 times higher performance in terms of encoding and decoding throughput as compared to the Intel 8-core system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.4
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• pp.307-311
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• 2004

This paper presents an efficient architecture that optimizes the design of SEED S-box using composite field arithmetic. SEED is the Korean standard 128-bit block cipher algorithm developed by Korea Information Security Agency. The nonlinear function S-box is the most costly operation in terms. of size and power consumption, taking up more than 30% of the entire SEED circuit. Therefore the S-box design can become a crucial factor when implemented in systems where resources are limited such as smart cards. In this paper, we transform elements in $GF(2^8)$ to composite field $GF(((2^2)^2)^2)$ where more efficient computations can be implemented and transform the computed result back to $GF(2^8)$. This technique reduces the S-box portion to 15% and the entire SEED algorithm can be implemented at 8,700 gates using Samsung smart card CMOS technology.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.339-342
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• 2000

This paper presented a FPGA design of SEED, which is the Korea standard 128-bit block cipher. In this work, SEED was designed technology- independently for other applications such as ASIC or core-based designs. Hence in case of changing the target of design, it is not necessary to modify design or need only minor modification to reuse the design. Since SEED algorithm requires a lot of hardware resources, each unit was designed only once and used sequentially. So, the number of gates was minimized and SEED algorithm was fitted in FPGA without additional components. It was confirmed that the rate of resource usage is about 80% in ALTERA 10KE and the SEED design operates in a clock frequency of 131.57 MHz and an encryption rate of 29 Mbps.

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.124-130
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• 2015

This paper presents a high performance HIGHT processor that can be applicable for CCM mode. In fact, HIGHT algorithm is a 64-bit block cipher. However, the proposed HIGHT extends the basic block length to 128-bit. The proposed HIGHT is operated as 128-bit block cipher and it can treat 128-bit block at once. Thus, it can be applicable for the various WSN applications that need fast and ultralight 128-bit block cipher, in particular, to be operated in CCM mode. In addition, the proposed HIGHT processor shares the common logics such as 128-bit key scheduler and control logics during encryption and decryption to reduce the area overhead caused by the extension of data block length. From the simulation results, the circuit area and power consumption of the proposed HIGHT are increases as 40% and 64% compared to the conventional 64-bit counterpart. However, the throughput of the proposed HIGHT can be up to two times as fast. Consequently, the proposed HIGHT is useful for USN and handheld devices based on battery as well as RFID tag the size of circuit is less than 5,000 gates.