• Journal of Broadcast Engineering
• /
• v.10 no.4 s.29
• /
• pp.576-586
• /
• 2005

This paper presents a new estimation and representation of a disparity map for stereo-based video communication systems. Several pixel-based and block-based algorithms have been proposed to estimate the disparity map. While the pixel-based algorithms can achieve high accuracy in computing the disparity map, they require a lost of bits to represent the disparity information. The bit rate can be reduced by the block-based algorithm, sacrificing the representation accuracy. In this paper, the block enclosing a distinct edge is divided into two regions and the disparity of each region is set to that of a neighboring block. The proposed algorithm employs accumulated histograms and a neural network to classify a type of a block. In this paper, we proved that the proposed algorithm is more effective than the conventional algorithms in estimating and representing disparity maps through several experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.1
• /
• pp.1-6
• /
• 2008

There are many possible representations in denoting both positive and negative numbers in the binary number system to be applicable to the complexity of the hardware implementation, arithmetic speed, appropriate application, etc. Among many possibilities, the signed-magnitude representation, which keeps one sign bit and magnitude bits separately, is intuitively appealing for humans, conceptually simple, and easy to negate by flipping the sign bit. However, in the signed-magnitude representation, the actual arithmetic operation to be performed may require magnitude comparison and depend on not only the operation but also the signs of the operands, which is a major disadvantage. In a simple conceptual approach, addition/subtraction of two signed-magnitude numbers, requires comparator circuits, selective pre-complement circuits, and the adder circuits. In this paper circuits to obtain the difference of two numbers are designed without adopting explicit comparator circuits. Then by using the difference circuits, a universal signed-magnitude adder/subtracter is designed for the most general operation on two signed numbers.

• Proceedings of the KIEE Conference
• /
• 2004.11c
• /
• pp.358-360
• /
• 2004

The digital images contain a significant amount of redundancy and require a large amount of data for their storage and transmission. Therefore, the image compression is necessary to treat digital images efficiently. The goal of image compression is to reduce the number of bits required for their representation. The image compression can reduce the size of image data using contractive mapping of original image. Among the compression methods, the mapping is affine transformation to find the block(called range block) which is the most similar to the original image. In this paper, we applied the neural network(SOM) in encoding. In order to improve the performance of image compression, we intend to reduce the similarities and unnecesaries comparing with the originals in the codebook. In standard image coding, the affine transform is performed with eight isometries that used to approximate domain blocks to range blocks.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.5
• /
• pp.775-783
• /
• 1990

In this paper we implemented the fast thinning unit by modifying the pipeline architecture which was proposed by Stanley R. Sternberg. The unit is useful in preprocessing such as image representation and pattern recognition etc. This unit is composed of interface part, local memory part, address generation part, thinning processing part and control part. In thinning processing part, we shortened the thinning part which performed by means of look up table using window mapping table. Thus we improved the weakness of SAP, in which the number of delay pipeline and window pipeline are equal to image column size. Two independent memorys using tri-state buffer enable the two direction flow of address generated by address generation part. This unit avoids the complexity of architecture and has flexibility of image size by means of simple modification of logic bits.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 2004.04a
• /
• pp.159-163
• /
• 2004

현재 복수개의 엘리베이터를 최적 제어하기 위해서 엘리베이터 군 제어 시스템이 사용되고 있다. 일반적인 엘리베이터 군 제어 시스템에서는 임의의 층에서의 호출(Hall Call)에 대해 복수개의 엘리베이터로부터 정보를 받는다. 다음으로 각 엘리베이터의 매력함수값을 산출, 매력함수들을 비교 한 후 가장 큰 값을 갖는 엘리베이터를 호출한 층으로 보내는 작업을 수행한다. 본 논문에서는 16개의 엘리베이터와 정렬 네트워크(Sorting Network)를 이용하여 각 엘리베이터들의 매력함수값의 비교를 수행하는 엘리베이터 군 제어부를 설계한다. 이를 통해 제어부에서 매력함수값들의 비교 연산에 소요되는 처리속도를 향상시킬 수 있다.

• Journal of Korea Multimedia Society
• /
• v.15 no.4
• /
• pp.485-491
• /
• 2012

This paper proposes 'Coding Unit Tree' based on quadtree efficiently with motion vector to represent splitting information of a Coding Unit (CU) in HEVC. The new international video coding, High Efficiency Video Coding (HEVC), adopts various techniques and new unit concept: CU, Prediction Unit (PU), and Transform Unit (TU). The basic coding unit, CU is larger than macroblock of H.264/AVC and it splits to process image-based quadtree with a hierarchical structure. However, in case that there are complex motions in CU, the more signaling bits with motion information need to be transmitted. This structure provides a flexibility and a base for a optimization, but there are overhead about splitting information. This paper analyzes those signals and proposes a new algorithm which removes those redundancy. The proposed algorithm utilizes a type code, a dominant value, and residue values at a node in quadtree to remove the addition bits. Type code represents a structure of an image tree and the two values represent a node value. The results show that the proposed algorithm gains 13.6% bit-rate reduction over the HM-1.0.

• Journal of IKEEE
• /
• v.19 no.3
• /
• pp.342-348
• /
• 2015

High speed implementation of digital filters is required in high data rate applications such as hard-wired wide band modem and high resolution video codec. Since the critical path of the digital filter is the MAC (multiplication and accumulation) circuit, the filter coefficient with sparse non-zero bits enables high speed implementation with adders of low hardware cost. Compressive sensing has been reported to be very successful in sparse representation and sparse signal recovery. In this paper a filter design method for digital FIR filters with CSD (canonic signed digit) coefficients using compressive sensing technique is proposed. The sparse non-zero signed bits are selected in the greedy fashion while pruning the mistakenly selected digits. A few design examples show that the proposed method can be utilized for designing sparse CSD coefficient digital FIR filters approximating the desired frequency response.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.6
• /
• pp.123-133
• /
• 2017

In this paper, we developed an optimal flicker-free control algorithm operating within 16 luminance implementation bits and 512 brightness implementation pulses irrespective of LPM(LED Pixel Matrix) module configuration on dynamic driving method of LED display system. As an implementation method, we turned the refresh rate up by increasing the number of scans through multiple shift-latches which were devised from conventional shift-latch scheme for full color representation. As a result, the LED display system of this method has no flicker phenomenon because of the novel refresh rate higher than 2,040[Hz] incomparable to 240~480[Hz] of conventional system.

• Journal of the Institute of Convergence Signal Processing
• /
• v.10 no.4
• /
• pp.289-293
• /
• 2009

This study proposes a novel double-base log encoder (DBLE) for flash Analog-to-Digital converters (ADCs). Analog inputs of flash ADCs are represented in logarithmic number systems with bases of 2 and 3 at the outputs of DBLE. A look up table stores the sets of exponents of base 2 and 3 values. This algorithm improves the performance of a DSP (Digital Signal Processor) system that takes outputs of a flash ADC, since the double-base log number representation does multiplication operation easily within negligible error range in ADC. We have designed and implemented 6 bits DBLE implemented with ROM (Read-Only Memory) architecture in a $0.18\;{\mu}m$ CMOS technology. The power consumption and speed of DBLE are better than the FAT tree and binary ROM encoders at the cost of more chip area. The DBLE can be implemented into SoC architecture with DSP to improve the processing speed.

• The KIPS Transactions:PartB
• /
• v.16B no.4
• /
• pp.309-318
• /
• 2009

The researches on the system that automatically records and retrieves one's everyday life is relatively actively worked recently. These systems, called personal memex or life log, usually entail dedicated devices such as SenseCam in MyLifeBits project. This research paid attention to the digital devices such as mobile phones, credit cards, and digital camera that people use everyday. The system enables a person to store everyday life systematically that are saved in the devices or the deviced-related web pages (e.g., phone records in the cellular phone company) and to refer this quickly later. The data collection agent in the proposed system, called MyMemex, collects the personal life log "web data" using the web services that the web sites provide and stores the web data into the server. The "file data" stored in the off-line digital devices are also loaded into the server. Each of the file data or web data is viewed as a memex event that can be described by 4W1H form. The different types of data in different services are transformed into the memex event data in 4W1H form. The memex event ontology is used in this transform. Users can sign in to the web server of this service to view their life logs in the chronological manner. Users can also search the life logs using keywords. Moreover, the life logs can be viewed as a diary or story style by converting the memex events to sentences. The related memex events are grouped to be displayed as an "episode" by a heuristic identification method. A result with high accuracy has been obtained by the experiment for the episode identification using the real life log data of one of the authors.