• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.6
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• pp.498-508
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• 1991

This thesis presents a performance analysis algorithm that estimates erro performance of individual links, at the bit level, in an end-to-end digital connection using the model of 3-statte MarKov chain. The link model proposed the burst error behavior of each individual link. It also presents a method to concateante several individual links and extract a model for end-to-end digital connection. This resulting end-to-end model can be used to calculate performance parameters such as bit error rate(BER) and block error(BLER) for any block size.

• ETRI Journal
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• v.33 no.5
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• pp.822-825
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• 2011

Level-encoded dual-rail (LEDR) has been widely used in onchip asynchronous interconnects supporting a 2-phase handshake protocol. However, it inevitably requires 2N wires for N-bit data transfers. Encoder and decoder circuits that perform an asynchronous 2-phase handshake protocol with only N wires for N-bit data transfers are presented for on-chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current-mode multiple valued logics. Using 0.25 ${\mu}m$ CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power-delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.949-952
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• 2000

A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.8
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• pp.1031-1036
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• 1999

A Hierarchical vector Quantization scheme is implemented and an optimal thresholding technique of quadtree segmentation for performing high quality low bit rate image compression is proposes. A mathematical model is constructed under the assumption that the standard deviations of sub-blocks are larger than or equal to the standard deviation of the upper level block which is generated by merging of sub-blocks. This thresholding technique based on the mathematical modeling allows producing about 1 dB improved performance in terms of PSNR at most ranges of bit rates over the quadtree coder, which is based on MSE for quadtree segmentation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.12
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• pp.1678-1684
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• 2018

Dental caries is one of the most popular oral disease. The aim of automatic dental cavity detection system is helping dentist to make accurate diagnosis. It is very important to separate cavity from the teeth in the detection system. In this paper, We compared two active contour algorithms, Snake and DRLSE(Distance Regularized Level Set Evolution). To improve performance, image is selected ROI(region of interest), then applied bilateral filter, Canny edge. In order to evaluate the algorithms, we applied to 7 tooth phantoms from incisor to molar. Each teeth contains two cavities of different shape. As a result, Snake is faster than DRLSE, but Snake has limitation to compute topology of objects. DRLSE is slower but those of performance is better.

• The Journal of Korea Robotics Society
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• v.18 no.3
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• pp.260-270
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• 2023

We introduce a novel Visual Inertial Odometry (VIO) algorithm designed to improve the performance of thermal-inertial odometry. Thermal infrared image, though advantageous for feature extraction in low-light conditions, typically suffers from a high noise level and significant information loss during the 8-bit conversion. Our algorithm overcomes these limitations by approximating a 14-bit raw pixel histogram into a Gaussian mixture model. The conversion method effectively emphasizes image regions where texture for visual tracking is abundant while reduces unnecessary background information. We incorporate the robust learning-based feature extraction and matching methods, SuperPoint and SuperGlue, and zero velocity detection module to further reduce the uncertainty of visual odometry. Tested across various datasets, the proposed algorithm shows improved performance compared to other state-of-the-art VIO algorithms, paving the way for robust thermal-inertial odometry.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.2
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• pp.206-216
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• 1986

In this paper, the moving distance and velocity of a single moving object are measured by sampling three frames in a two-dimensional line sequence image. The brightness of each frame is analyzed, and the bit data of their pixel are rearranged so that the difference image may be extracted. The parameters for recognition of the object are the gray level of the object, the number of vertex points and the distance between the vertex points. The moving distance obtained from the coordinate which is constructed by the bit processing of the data in the memory map of a microcomputer, and the moving velocity is obtained from the moving distance and the time interval between the first and second sampled frames.

• ETRI Journal
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• v.36 no.5
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• pp.876-879
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• 2014

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.11
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• pp.1959-1975
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• 2011

Adaptive Bit Loading (ABL) in Multiple-Input Multiple-Output Orthogonal Frequency-Division Multiplexing (MIMO-OFDM) is often used to achieve the desired Bit Error Rate (BER) performance in wireless systems. In this paper, we discuss some of the bit loading algorithms, compare them in terms of the BER performance, and present an effective and concise Adaptive Grouped Loading (AGL) algorithm. Furthermore, we propose a "weight factor" for loading algorithm to converge rapidly to the final solution for various data rate with variable Signal to Noise Ratio (SNR) gaps. In particular, we consider the bit loading in near optimal Singular Value Decomposition (SVD) based MIMO-OFDM system. While using SVD based system, the system requires perfect Channel State Information (CSI) of channel transfer function at the transmitter. This scenario of SVD based system is taken as an ideal case for the comparison of loading algorithms and to show the actual enhancement achievable by our AGL algorithm. Irrespective of the CSI requirement imposed by the mode of the system itself, ABL demands high level of feedback. Grouped Loading (GL) would reduce the feedback requirement depending upon the group size. However, this also leads to considerable degradation in BER performance. In our AGL algorithm, groups are formed with a number of consecutive sub-channels belonging to the same transmit antenna, with individual gains satisfying predefined criteria. Simulation results show that the proposed "weight factor" leads a loading algorithm to rapid convergence for various data rates with variable SNR gap values and AGL requires much lesser CSI compared to GL for the same BER performance.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.