• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.7C
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• pp.624-632
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• 2005

We consider an adaptive bit-loading technique for bit interleaved coded modulation-orthogonal frequency division multiplexing(BICM-OFDM) systems. By adjusting transmission parameter of each subcarrier adaptively depending on the subchannel state, the performance of OFDM system can be improved dramatically. In this paper, the number of bits for each subcarrier is allocated to minimize bit error rate keeping the constant throughput for the adaptive transmission technique of BICM-OFDM system which can be applied to real time transmission. Also, We use the discrete Lagrange multiplier method to get the optimum solution under the integer bit allocation constraint. Simulation results show that computational amount of the proposed bit allocation technique is not high and BICM-OfDM system using the proposed technique can get the SNR gain by 2$\~$3 dB over nonadaptive one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.1
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• pp.24-30
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• 2006

The Controller Area Network (CAN) is being widely used for real-time control application and small-scale distributed computer controller systems. When the stuff bits are generated by bit-stuffing mechanism in the CAN network, it causes jitter including variations in response time and delay In order to eliminate this jitter, stuff bits must be controlled to minimize the response time and to reduce the variation of data transmission time. This paper proposes the method to reduce the stuff bits by restriction of available identifier and bit mask using exclusive OR operation. This da manipulation method are pretty useful to the real-time control strategy with respect to performance. However, the CAN may exhibit unfair behavior under heavy traffic conditions. When there are both high and low priority messages ready for transmission, the proposed precedence priority filtering method allows one low priority message to be exchanged between any two adjacent higher priority messages. In this way, the length of each transmission delays is upper bounded. These procedures are implemented as local controllers for the ISHURO(Inha Semvung Humanoid Robot).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.483-485
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• 2010

A 200kS/s 10-bit successive approximation(SA) ADC with a rail-to-rail input range is proposed. The proposed SA ADC consists of DAC, comparator, and successive approximation register(SAR) logic. The folded-type capacitor DAC with the boosted NMOS switches is used to reduce the power consumption and chip area. Also, the time-domain comparator which uses a fully differential voltage-to-time converter improves the PSRR and CMRR. The SAR logic uses the flip-flop with a half valid window, it results in the reduction of the power consumption and chip area. The proposed SA ADC is designed by using a $0.18{\mu}m$ CMOS process with 1V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1623-1632
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• 2004

In this paper, we analyze the performance of linear search and bit reversal search algorithms based on the single-dwell serial search for rapid UWB (Ultra Wide Band) signal acquisition in typical indoor wireless channel environments. Simulation results according to bin spacing and frame interval in IEEE 802.15 Task Group 3a UWB indoor wireless channels show that bit reversal search algorithm achieves much smaller normalized mean acquisition time than linear search algorithm. In particular, it is found that the normalized mean acquisition time of the bit reversal search according to the range of searching termination interval closely matches the ideal case. In addition, we observe that the acquisition performance of bit reversal search algorithm becomes much better as bin spacing gets finer.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.12
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• pp.2324-2328
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• 2010

In this paper we proposed a new algorithm that can reduce the open-loop pitch estimation time of G.723.1. The time domain cross-correlation method is simple but has long processing time by recursive multiplication. For reduction of processing time, we use the method that compute the cross-correlation by multiplying the Fourier value of speech by it's complex conjugate. Also, we can reduce the processing time by omitting the bit-reversing of FFT and IFFT for time-frequency domain transform. As a result, the processing time of improved hybrid domain cross-correlation algorithm is reduced by 67.37% of conventional time domain cross-correlation.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.715-718
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• 1998

본 논문에서는 시분할 구조와 1.5bit 디지털 에러보상을 사용하여 작은 면적을 갖는 저 전압, 저전력 10bit 1㎒ 사이클릭 A/D 변환기를 제안하였다. 제안된 사이클릭 A/D 변환기는 시분할 구조를 사용함으로서 변환속도의 향상과 저 전력 특성을 가질 수 있었으며 1.5bit 디지털 에러 보상을 사용함으로서 10bit의 고해상도와 저 전력 특성을 구현할 수 있었다. 제안된 사이클릭 A/D 변환기는 0.6㎛ CMOS Nwell 공정 parameter로 simulation 하였으며 layout 결과 칩면적은 1.1㎜×0.8㎜ 이며 이는 비슷한 성능을 갖는 다른 A/D 변환기에 비하여 매우 작은 크기이다. 제안된 사이클릭 A/D 변환기는 3V의 전원전압에 1.6㎽의 전력소모를 갖는다. Matlab simulation 결과 INL, DNL은 각각 0.6LSB, 0.7LSB 이하의 값을 보였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.215-217
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• 2006

This paper presents an area efficient 8-bit current digital to analog convector (DAC) which is applied to 240 channels Active Matrix - Organic Light Emitting Diode (AMOLED) data driver. The proposed circuit constitutes 4-bit binary weighted current DAC and 4-bit switched capacitor cyclic DAC. The proposed DAC has about 70% smaller area than that of the typical binary weighted current DAC. We overcome sampling time by reducing the number of repetition phases so that it can display 8-bit gray scale image.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.726-742
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• 2000

A novel rte control algorithm consisting of two major components, i.e. a variable encoding frame rate method and a hybrid DCT/wavelet I-frame coding scheme, is proposed in this work for low bit rate video coding. Most existing rate control algorithms for low bit rate video focus on bit allocation at the macroblock level under a constant frame rate assumption. The proposed rate control algorithm is able to adjust the encoding frame rate at the expense of tolerable time-delay. Furthermore, an R-D optimized hybrid DCT/wavelet scheme is used for effective I-frame coding. The new rate-control algorithm attempts to achieve a good balance between spatial quality and temporal quality to enhance the overall human perceptual quality at low bit rates. It is demonstrated that the rate control algorithm achieves higher coding efficiency at low bit rates with a low additional computational cost. The variable frame rate method and hybrid I-frame coding scheme are compatible with the bi stream structure of H.263+.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.