• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.717-720
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• 2007

This paper presents a novel scheme that quickly searches for the optimal direction of multiple directional antennas, and locks on to it for high-speed millimeter wavelength transmissions, when communications to another antenna directional are disconnected. The proposed method utilizes a modified genetic algorithm, which selects a superior initial group through preprocessing in order to solve the local solution in genetic algorithm. TDD (Time Division Duplex) is utilized as the transfer method and data controller for the antenna. Once the initial communication is completed for the specific number of individuals, no longer antenna's data will be transmitted nil each station processes GA in order to produce the next generation. After reproduction, individuals of the next generation become the data, and communication between each station is made again. In order to verify the effectiveness of the proposed system, simulation results of 1:1, 1:2, 1:5 directional antennas and experiment results of 1:1 directionalantennas confirmed the efficiency of the proposed method. The 16bit split is 8bit, but it has similar performance as 16bit gene.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.76-81
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• 2009

A novel design method of time-interleaved subranging ADC is presented. We use the bisection method to let only half of comparators in typical subranging ADC working in every clock cycle. Thus, we are able to reduce the number of comparators by half. It is possible to reduce the die size. An example of 8-bit time-interleaved subranging ADC operates at 40MHz sampling rate and 1.8V supply voltage is demonstrated. The power consumption of the proposed circuit is only 10mV with SPECTRE simulation. Compared with the typical subranging ADC, our bisection method is able to reduce up to 40% in die size.

• Journal of Broadcast Engineering
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• v.13 no.6
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• pp.804-816
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• 2008

In this paper, we propose an adaptive rate control in frame-level for real-time H.264/AVC. For given QP, bits according to video characteristics, and current frame is close correlation between the adjacent frames. Using the statistical characteristic, we obtain change of occurrence bit about QP to apply the bit amount by QP from the video characteristic and applied in the estimated bit amount of the current frame. In addition, we use weight with QP and occurrence bit amount that is statistical information of encoded previous frames. Simulation results show that the proposed rate control scheme achieves time saving of more than 99% over JM 12.1 rate control algorithm. Nevertheless, PSNR and bit rate were almost same as the performances of JM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.49-54
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• 2008

In cryptosystems based on finite fields, a modular multiplication operation is the most crucial part of finite field arithmetic. Also, in multipliers with resource constrained environments, bit-serial output structures are used in general. This paper proposes two efficient bit-serial output multipliers with the polynomial basis representation for irreducible trinomials. The proposed multipliers have lower time complexity compared to previous bit-serial output multipliers. One of two proposed multipliers requires the time delay of $(m+1){\cdot}MUL+(m+1){\cdot}ADD$ which is more efficient than so-called Interleaved Multiplier with the time delay of $m{\cdot}MUL+2m{\cdot}ADD$. Therefore, in elliptic curve cryptosystems and pairing based cryptosystems with small characteristics, the proposed multipliers can result in faster overall computation. For example, if the characteristic of the finite fields used in cryprosystems is small then the proposed multipliers are approximately two times faster than previous ones.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2C
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• pp.161-171
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• 2010

In this paper, we propose an adaptive rate control in Unit-level for real-time H.264/AVC. For given QP, bits according to video characteristics, and current frame is close correlation between the adjacent frames. Using the statistical characteristic, we obtain change of occurrence bit about QP to apply the bit amount by QP from the video characteristic and applied in the estimated bit amount of the each unit of current frame. In addition, we use weight with QP and occurrence bit amount that is statistical information of encoded previous frames. Simulation results show that the proposed rate control scheme achieves time saving of more than 99% over JM 12.1 rate control algorithm. Nevertheless, PSNR and bit rate were almost same as the performances of JM.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.999-1005
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• 2008

RFID(Radio Frequency IDintification) leader is collision of data, when recognizing the multiple tag the inside area. This collision became the cause which delays the tag recognition time of the leader. The protocol which prevents the delay of tag recognition time of the leader the place where representative it uses QT(Query Tree) algorithms, it uses a collision bit position from this paper and are improved QT-MTC(Query Tree with Multi-Tag Cognition) algorithms which it proposes. This algorithm stored the bit position which bit possibility and the collision where the collision happens occurs in the stack and goes round a tree the number of time which, it reduced could be identified two tags simultaneously in order, it was planned. A result of performance analysis, It compared in QT protocols and the this algorithm against the tag bit which is continued a high efficiency improvement effect was visible.

• Journal of IKEEE
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• v.24 no.4
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• pp.1058-1063
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• 2020

This paper proposes a 12-bit SAR A/D(Successive Approximation Register Analog-to-Digital) converter that operates at low power for bio-signal and sensor signal processing. The conventional SAR A/D converter utilized the reduction of the dynamic current, which resulted in reducing total power consumption. In order to solve the limitation of the sampling time due to charging/discharging of the capacitor for reducing dynamic current, the different sampling time on the C-DAC bit switch operation was applied to reduce the dynamic current. In addition, lowering the supply voltage of the digital block to 0.6V led to 70% reduction of the total power consumption of the proposed ADC. The proposed SAR A/D was implemented with CMOS 65nm process 1-poly 6-metal, operates with a supply voltage of 1.2V. The simulation results demonstrate that ENOB, DNL/INL, power consumption and FoM are 10.4 bits, ±0.5LSB./±1.2LSB, 31.2uW and 2.8fJ/step, respectively.

• Journal of the Korea Society for Simulation
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• v.18 no.2
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• pp.9-17
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• 2009

A face database has contained a large amount of facial information data since face recognition was widely used. With the increase of facial information data, the face recognition based on distributed processing method has been noticed as a major topic. In existing studies, there were lack of discussion about the transferring method for large data. So, we proposed a fuzzy logic-based bit compression rate selection method for distributed face recognition. The proposed method selects an effective bit compression rate by fuzzy inference based on face recognition rate, processing time for recognition, and transferred bit length. And, we compared the facial recognition rate and the recognition time of the proposed method to those of facial information data with no compression and fixed bit compression rates. Experimental results demonstrates that the proposed method can reduce processing time for face recognition with a reasonable recognition rate.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.733-736
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• 1999

In this Paper, Bit selectable and Bi-directional Interface Port is described, which can communicate data with the peripheral devices. Specially A description of the asynchronous design method is given to remove the clock skew phenomenon and the output asynchronous control method which finds the optimal clock and controls all the enable signal of the output pins at the same time is presented. Using this technique interface ports have delay time of less-than 0.5㎱.

• Journal of Electrical Engineering and information Science
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• v.3 no.3
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• pp.300-305
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67 ns access time for a 3-V power supply. It was achieved using the sense amplifier with multiple point sensing scheme and highs peed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5m double-polysilicon and triple-metal CMOS process technology. A die size is 1.78${\times}$mm2.13mm.