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Fast Bit-Serial Finite Field Multipliers  

Chang, Nam-Su (Graduate School of Information Management and Security, Korea University)
Kim, Tae-Hyun (Graduate School of Information Management and Security, Korea University)
Lee, Ok-Suk (Graduate School of Information Management and Security, Korea University)
Kim, Chang-Han (School of Information & Communication systems, Semyung University)
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Abstract
In cryptosystems based on finite fields, a modular multiplication operation is the most crucial part of finite field arithmetic. Also, in multipliers with resource constrained environments, bit-serial output structures are used in general. This paper proposes two efficient bit-serial output multipliers with the polynomial basis representation for irreducible trinomials. The proposed multipliers have lower time complexity compared to previous bit-serial output multipliers. One of two proposed multipliers requires the time delay of $(m+1){\cdot}MUL+(m+1){\cdot}ADD$ which is more efficient than so-called Interleaved Multiplier with the time delay of $m{\cdot}MUL+2m{\cdot}ADD$. Therefore, in elliptic curve cryptosystems and pairing based cryptosystems with small characteristics, the proposed multipliers can result in faster overall computation. For example, if the characteristic of the finite fields used in cryprosystems is small then the proposed multipliers are approximately two times faster than previous ones.
Keywords
Bit-Serial Multiplier; Elliptic Curve Cryptosystem; Pairing Based Cryptosystem; Hardware Architecture;
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