• Title/Summary/Keyword: Bit error

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A Power-adjustable Fully-integrated CMOS Optical Receiver for Multi-rate Applications

  • Park, Kangyeob;Yoon, Eun-Jung;Oh, Won-Seok
    • Journal of the Optical Society of Korea
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    • v.20 no.5
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    • pp.623-627
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    • 2016
  • A power-adjustable fully-integrated CMOS optical receiver with multi-rate clock-and-data recovery circuit is presented in standard 65-nm CMOS technology. With supply voltage scaling, key features of the optical receiver such as bandwidth, power efficiency, and optical sensitivity can be automatically optimized according to the bit rates. The prototype receiver has −23.7 dBm to −15.4 dBm of optical sensitivity for 10−9 bit error rate with constant conversion gain around all target bit rates from 1.62Gbps to 8.1 Gbps. Power efficiency is less than 9.3 pJ/bit over all operating ranges.

The Bit Synchronizer of The Frequency Hopping System using Adaptive Window Filter (적응윈도우 필터를 이용한 주파수 도약용 비트 동기방식)

  • 김정섭;황찬식
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.8B
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    • pp.1532-1539
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    • 1999
  • In this paper, we propose a bit synchronizer which is suitable for frequency hopping systems. The proposed bit synchronizer is an ADPLL in which the digial loop filter is combined with an error symbol detecting circuit using an adaptive window. Suppressing the tracking process when hop mute and impulse noises are detected improves the performance of the digital loop filter and enhances the probability of the frequency hopping system. The simulation results demonstrate an improved performance of the proposed bit synchronizer compared with existing ones.

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Optimal Relay Selection and Power Allocation in an Improved Low-Order-Bit Quantize-and-Forward Scheme

  • Bao, Jianrong;He, Dan;Xu, Xiaorong;Jiang, Bin;Sun, Minhong
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.10 no.11
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    • pp.5381-5399
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    • 2016
  • Currently, the quantize-and-forward (QF) scheme with high order modulation and quantization has rather high complexity and it is thus impractical, especially in multiple relay cooperative communications. To overcome these deficiencies, an improved low complex QF scheme is proposed by the combination of the low order binary phase shift keying (BPSK) modulation and the 1-bit and 2-bit quantization, respectively. In this scheme, the relay selection is optimized by the best relay position for best bit-error-rate (BER) performance, where the relays are located closely to the destination node. In addition, an optimal power allocation is also suggested on a total power constraint. Finally, the BER and the achievable rate of the low order 1-bit, 2-bit and 3-bit QF schemes are simulated and analyzed. Simulation results indicate that the 3-bit QF scheme has about 1.8~5 dB, 4.5~7.5 dB and 1~2.5 dB performance gains than those of the decode-and-forward (DF), the 1-bit and 2-bit QF schemes, at BER of $10^{-2}$, respectively. For the 2-bit QF, the scheme of the normalized Source-Relay (S-R) distance with 0.9 has about 5dB, 7.5dB, 9dB and 15dB gains than those of the distance with 0.7, 0.5, 0.3 and 0.1, respectively, at BER of $10^{-3}$. In addition, the proposed optimal power allocation saves about 2.5dB much more relay power on an average than that of the fixed power allocation. Therefore, the proposed QF scheme can obtain excellent features, such as good BER performance, low complexity and high power efficiency, which make it much pragmatic in the future cooperative communications.

A 10-bit 100 MSPS CMOS D/A Converter with a Self Calibration Current Bias Circuit (Self Calibration Current Bias 회로에 의한 10-bit 100 MSPS CMOS D/A 변환기의 설계)

  • 이한수;송원철;송민규
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.11
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    • pp.83-94
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    • 2003
  • In this paper. a highly linear and low glitch CMOS current mode digital-to-analog converter (DAC) by self calibration bias circuit is proposed. The architecture of the DAC is based on a current steering 6+4 segmented type and new switching scheme for the current cell matrix, which reduced non-linearity error and graded error. In order to achieve a high performance DAC . novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. Experimental result show that SFDR is 60 ㏈ when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46 mW at a 3.3 Volt single power supply and occupies a chip area of 1350${\mu}{\textrm}{m}$ ${\times}$750${\mu}{\textrm}{m}$.

Reliable Data Transmission Based on Erasure-resilient Code in Wireless Sensor Networks

  • Lei, Jian-Jun;Kwon, Gu-In
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.4 no.1
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    • pp.62-77
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    • 2010
  • Emerging applications with high data rates will need to transport bulk data reliably in wireless sensor networks. ARQ (Automatic Repeat request) or Forward Error Correction (FEC) code schemes can be used to provide reliable transmission in a sensor network. However, the naive ARQ approach drops the whole frame, even though there is a bit error in the frame and the FEC at the bit level scheme may require a highly complex method to adjust the amount of FEC redundancy. We propose a bulk data transmission scheme based on erasure-resilient code in this paper to overcome these inefficiencies. The sender fragments bulk data into many small blocks, encodes the blocks with LT codes and packages several such blocks into a frame. The receiver only drops the corrupted blocks (compared to the entire frame) and the original data can be reconstructed if sufficient error-free blocks are received. An incidental benefit is that the frame error rate (FER) becomes irrelevant to frame size (error recovery). A frame can therefore be sufficiently large to provide high utilization of the wireless channel bandwidth without sacrificing the effectiveness of error recovery. The scheme has been implemented as a new data link layer in TinyOS, and evaluated through experiments in a testbed of Zigbex motes. Results show single hop transmission throughput can be improved by at least 20% under typical wireless channel conditions. It also reduces the transmission time of a reasonable range of size files by more than 30%, compared to a frame ARQ scheme. The total number of bytes sent by all nodes in the multi-hop communication is reduced by more than 60% compared to the frame ARQ scheme.

Evaluation of communication reliability of a test-bed networked to the home appliances with PLC modems for the Internet accessed home automation

  • Ahn, Nam-Ho;Chang, Tae-Gyu;Kim, Hoon
    • Proceedings of the IEEK Conference
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    • 2002.07a
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    • pp.591-594
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    • 2002
  • This paper presents a systematic method of probing channel characteristics and communication reliabilities of home power line communication network applied to the Internet accessed control of home appliances. The effects of the three performance deteriorating factors, i.e., additive noise, channel attenuation, and intersymbol interference, can be systematically measured by applying the channel probing waveform in the frequency range from 100㎑ to 450㎑. Probability of bit error is derived with the probed channel parameters of the signal attenuation, noise and signal-to-interference ratio read in the frequency domain. The agreement between the derived probability of bit ewer and the measured probability of bit error support the validity of the proposed approach of probing home power line channel characteristics. The experimental results performed with the constructed test-bed applying the Proposed channel probing method and the operation reliability measurement of the overall networked system also support the feasibility of commercially deploying the PLC modem installed home appliances and their services for the Internet accessed home automation in densely populated residential apartment complexes.

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A Study on the Implementation of DS/SS Power Line Communication System for Burst-Format Data Transmission (버스트형 데이터 전송을 위한 DS/SS 전력선 통신시스템의 실현에 관한 연구)

  • 강병권;이재경;신광영;황금찬
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.16 no.11
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    • pp.1054-1062
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    • 1991
  • In this paper a communication system using direct sequence spread spectrum (DS/SS) technique is constructed to transmit burst format data over power line channel with impulsive noise and narrowband interferences. Fast code synchronization is acquired by digital matched filter and data decision is accomplished by sampling pulses. In order to examine the performance of the power line communication system, but error rate and packet loss rate are measured over the simulation channel with various noise sources. When the packet composed of 1-bit preamble and 63-bit data is transmitted under very high burst impulsive noise, the bit error rate is about 10$^3$-10$^4$ and the packet loss rate is below 0.07.

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Simple Signal Detection Algorithm for 4+12+16 APSK in Satellite and Space Communications

  • Lee, Jae-Yoon;Yoon, Dong-Weon;Hyun, Kwang-Min
    • Journal of Astronomy and Space Sciences
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    • v.27 no.3
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    • pp.221-230
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    • 2010
  • A 4+12+16 amplitude phase shift keying (APSK) modulation outperforms other 32-APSK modulations in a nonlinear additive white Gaussian noise (AWGN) channel because of its intrinsic robustness against AM/AM and AM/PM distortions caused by the nonlinear characteristics of a high-power amplifier. Thus, this modulation scheme has been adopted in the digital video broadcasting-satellite2 European standard. And it has been considered for high rate transmission of telemetry data on deep space communications in consultative committee for space data systems which provides a forum for discussion of common problems in the development and operation of space data systems. In this paper, we present an improved bits-to-symbol mapping scheme with a better bit error rate for a 4+12+16 APSK signal in a nonlinear AWGN channel and propose a simple signal detection algorithm for the 4+12+16 APSK from the presented bit mapping.

The Performance Analysis of the Concatenated Coding System using Punctured Convolutional Code in the Satellite Channel (위성 채널에서 펑쳐드 콘볼루션 부호를 이용한 직렬연결 부호 시스템의 성능 분석)

  • 정호영;강창언
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.6
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    • pp.1115-1125
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    • 1994
  • In this paper, an efficient concatenated coding scheme under the satellite channel is presented. The performance of this scheme in terms of bit error rate versus energy per information bit over white gaussian noise power density E/N has been evaluated via computer simulation as a function of various system parameters. To achieve accuracy in simulation results, the distortions caused from the satellite channel, such as the nonlinearity of the TWTA(traveling wave tube amplifier), signal distortions of the input and output filters, has been considered. The simulation results show that, through using the 2/3 punctured convolutional code as the inner code of the concatenated code system, the coding rate can be improved more over 16%, while maintaining the same system complexity and bit error performance.

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Performance Analysis of a New Adaptive PTS Scheme for Reducing the PAPR and High Speed Processing in OFDM Systems (OFDM 시스템에서 PAPR기 감소와 고속처리를 위한 새로운 적응형 PTS 기법의 성능분석)

  • 채주호;임연주;박상규
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.28 no.9A
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    • pp.710-716
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    • 2003
  • OFDM is a very attractive technique for achieving high-bit-rate data transmission and high spectrum efficiency. However one of disadvantages of OFDM signal is the high PAPR characteristic when multicarriers are added up coherently. In this paper, we propose an adaptive PTS scheme using two threshold levels for PAPR reduction and reducing the amount of PAPR calculations with clipping scheme. Simulation results show that it is almost same between average bit error rate performance of the proposed scheme and that of a conventional scheme. Also, we obtain a great performance gain in the amount of calculations compared to the conventional scheme. Therefore, proposed system has a good performance in data processing time in OFDM wireless communication systems.