• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.7
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• pp.1-8
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• 1997

In this paper, Stokes parameters which represent the states of polarization of transmitted light are determined by potential function, which is used to obtain signals points in a multidimensional Euclidean structure. And performance of multilevel polarization shift keying(POLSK) system using the obtained parameters is also represented and analyzed. As results, bit error rate of multilevel POLSK system using the potential function is shown to be lower than the conventional one using the distance matrix. And as number of levels increases, the number of photons per bit for bit error rate of 10$^{-9}$ is also increased linearly. The multilevel POLSK system, therefore, is an energy efficient modulation technque as compared with the convnetional ones.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.2
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• pp.22-30
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• 1998

In this paper, we analyze CDMA systems using M-orthogonal spreading codes. We assume that each user one set of M-orthogonal spreading codes allocated randomaly. The effect of multiple access interference from the reference and adjacent cells is considered slowly frequency selective rayleigh fading channels. and the adjacent cells interference is considered toanalyze the system performance. We calculate bit error rate and the maximum number of users whoe can communicate simulaneously within a cell by suing Rake receiver. By comparing CDMA systemwhich transmits 1 bit/spreding code, our system shows bit error rate decreases as M increases under the same bandwidth and infromation rate.

• Journal of Biomedical Engineering Research
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• v.7 no.1
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• pp.53-58
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• 1986

This paper represent the design of a digital modem which transmits the ECG data from an ambulatory arrhythmia monitor over the telephone lines to a large hospital for the instantaneous interpretations. The digital modem provides on-line communications between the patient and the central computer located near cardiologists. For commercial telephone lines, the transmitting error rates of the digital modem were measured 200 times at a speed of 300 baud. In those measurements, the block errors-results, due to the misinterpretation of start and stop bits, did not occur, The data bit errors which were due to a single bit interpreted incorrectly were 0.78 (bits/10 ) . Since the acceptable data bit error limit is 10 per 106 bits transmitted, the digital modem designed in this paper can be used for the clinical applications without any difficulty.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.1
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• pp.13-22
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• 1991

In this paper we designed 2 bit ECC(Error Checking and Correction) circuit using Single Layer Perceptron type neural networks. We used (11, 6) block codes having 6 data bits and 8 check bits with appling cyclic hamming codes. All of the circuits are layouted by CMOs 2um double metal design rules. In the result of circuit simulation, 2 bit ECC circuit operates at 67MHz of input frequency.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.4
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• pp.443-448
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• 2014

Soft errors in memory devices that caused by radiation are the main threat from a reliability point of view. This threat can be commonly overcome with the combination of SEC (Single-Error Correction) codes and scrubbing technique. The interleaving architecture can give memory devices the ability of tolerating these soft errors, especially against multiple-bit soft errors. And the interleaving distance plays a key role in building the tolerance against multiple-bit soft errors. This paper proposes a reliability model of an interleaved memory device which suffers from multiple-bit soft errors and are protected by a combination of SEC code and scrubbing. The proposed model shows how the interleaving distance works to improve the reliability and can be used to make a decision in determining optimal scrubbing technique to meet the demands in reliability.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.3
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• pp.164-170
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• 2003

This paper proposes a novel method to detect Furon's asymmetric watermark by using a correlation detector that is mathematically tractable and simple. The performance of the proposed method is tested under various conditions. The experimental results matched the theoretical results well, showing that the correlation detector can indeed be used for the detection of asymmetric watermark. The proposed detector is aplied to both single and multiple bit embedded watermark. Bit error rate (BER), obtained from the experiment, was compared to the one obtained from the theory. As the embedded information increases, the BER of the Furon's asymmetric watermarking method also increases rapidly.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.31-37
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• 2020

We present an approximate DRAM architecture for energy-efficient deep learning. Our key premise is that by bounding memory errors to non-critical information, we can significantly reduce DRAM refresh energy without compromising recognition accuracy of deep neural networks. To validate the key premise, we make extensive Monte-Carlo simulations for several well-known convolutional neural networks such as LeNet, ConvNet and AlexNet with the input of MINIST, CIFAR-10, and ImageNet, respectively. We assume that the highest-order 8-bits (in single precision) and 4-bits (in half precision) are protected from retention errors under the proposed architecture and then, randomly inject bit-errors to unprotected bits with various bit-error-rates. Here, recognition accuracies of the above convolutional neural networks are successfully maintained up to the 10^-5-order bit-error-rate. We simulate DRAM energy during inference of the above convolutional neural networks, where the proposed architecture shows the possibility of considerable energy saving up to 10 ~ 37.5% of total DRAM energy.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.10 no.3
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• pp.147-152
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• 1985

The error-trapping decoder is constructed for the (7, 3) Reed-Solomon code. The syndrome resister is constructed with the encoder and the substanial test logic circuits. The element of GF(8) is represented by the triple D-flip-floops. The hardware is constructed. And it is controlled by the micro computer(Apple II). The time for the encoding and the decoding were $350\musecs and 910u secs respectively. The experimental results show that the two symbol errors were corrected and 4-bit-binary-burst errors were also corrected.