• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.11
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• pp.97-104
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• 2010

This paper presents a high performance 32-bit single core AES architecture. The proposed architecture employs a 5-stage pipeline: four stages in the ShiftRows/InvShiftRows module, and one stage in the MixColumn/InvMixColumn module. Circuit size reduction has been achieved through merging of the shift rows and inverse shift rows. The mix column and inverse mix column share the same resources. Three 32-bit registers replace the conventional ten 32-bit registers in the RCON architecture. The proposed architecture has been implemented in Verilog HDL, and yields 415 Mbits/s throughput with the circuit size of 13764 gate equivalents on the 0.18um CMOS process technology. This high performance architecture is suitable for wireless network router applications.

• Journal of the Korea Society of Computer and Information
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• v.17 no.11
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• pp.1-10
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• 2012

In this paper, the extension of the addressing mode in the 16-bit Thumb instruction set architecture is proposed to improve the performance of 16-bit Thumb code. The key idea of the proposed approach is the introduction of new addressing modes for more frequent instructions by using the saved bits from the reduction of the register fields in less frequently used instructions. The proposed approach adopts efficient addressing modes from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To speed up access to a data list, scaled register offset addressing mode and post-indexed addressing mode are introduced for load and store instructions. Experiments show that the proposed approach improves performance by an average of 8.5% when compared to the conventional approach.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10a
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• pp.415-417
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• 2003

본 논문에서는 유한 필드 GF(2$^{m}$ ) 상에서 A$B^2$연산을 수행하는 디지트 시리얼(digit-serial) 시스톨릭 구조를 제안하였다. 제안한 구조는 디지트 크기를 적당히 선택했을 때, 비트-패러럴(bit-parallel) 구조에 비해 적은 하드웨어를 사용하고 비트-시리얼(bit-serial) 구조에 비해 빠르다 또한, 제안한 디지트 시리얼 구조에 파이프라인 기법을 적용하면 그렇지 않은 구조에 비해 m=160, L=2 일 때 공간-시간 복잡도가 10.9% 적다.

• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06b
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• pp.214-216
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• 2012

BIT(Built-in Test)란 소프트웨어와 하드웨어의 기능 및 상태를 진단하고 오류에 대응하기 위한 방법론으로 빠른 오류 대처가 있어야 하는 다양한 분야에서 사용되고 있다. 현업에서의 BIT는 도메인의 특성에 따라 고려해야 하는 요소가 많으므로 각 도메인에 맞춰 구조화되지 않은 형태로 개발되고 있다. 따라서 기존 개발 방법론은 반복적인 작업이 수반되며 적용 환경 및 상활에 따라 변화하는 부분을 매번 새로 개발하기 위해 많은 인력과 시간이 필요하다는 문제점을 가진다. 이를 해결하기 위하여 본 논문에서는 개선된 BIT 개발 프로세스를 제안한다. 제안하는 프로세스는 BIT 처리 과정을 일반화하여 명세하고 이를 활용하여 BIT 처리 코트를 자동 생성한다. 그리고 BIT 코드를 검증할 수 있는 시뮬레이션 환경을 제공한다. 이를 통해 BIT 처리 구조 개발 과정의 편의성과 생산성을 향상하고 BIT 처리 구조의 유연성과 확장성 그리고 안정성을 높일 수 있다.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.175-179
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• 2005

A novel, simple and broadband $180^{\circ}$ bit X-band phase shifter was proposed and fabricated in a standard micromachining process. It is composed of two $90^{\circ}$ parallel-coupled lines; one of which is shorted and the other is grounded. Design equations for the proposed $180^{\circ}$ bit phase shifter are derived by the method of even and odd mode analysis. Based on design equations, $180^{\circ}$ bit phase shifter was designed and fabricated to operate from 7 to 13 GHz with ${\pm}5^{\circ}$ of phase deviation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.11a
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• pp.3-5
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• 2000

1.8V,4Gb DDR SDRAM설계 및 제작을 수행하였다. DRAM동작 시 발생하는 Bit Line간 CouplingNoise를 보상하기 위한 Twisted Open Bit Line 구조를 제안하였다. Low Voltage Operation으로 인한 Bit Line Sense Amplifier 의 동작 저하를 보상하기 위한 BL S/A Pre-Sensing 방식 및 Reference Bit Line Voltage Calibration 구조를 제안하였다. Chip면적 증가로 인한 동작속도 감소의 보상을 위해 Repeater Driver 구조를 Core 및 Periphery Circuit에 적용하여 동작 대비 Chip 면적의 증가를 최소화 하도록 하였다.

• Journal of KIISE:Information Networking
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• v.28 no.2
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• pp.262-276
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• 2001

Recently much research for developing forwarding table that support fast router without employing both special hardware and new protocols. This article introduces a new forwarding data structure based on the software to enable forwarding lookup to be penormed at giga-bit speed. The forwarding table is known as a bottleneck of the routers penormance due to its high complexity proportional to the forwarding table size. The recent research that based on the software uses a Patricia trie and its variants. and also uses a hash function with prefix length key and others. The proposed forwarding table structure construct a forwarding table by the bit stream array in which it constructs trie from routing table prefix entries and it represents each pointer pointing the child node and the associated forwarding table entry with one bit The trie structure and routing prefix pointer need a large memory when representing those by linked-list or array. but in the proposed data structure, the needed memory size is small enough since it represents information with one bit. Additionally, by use a lookup method that start searching at desired middle level we can shorten the search path. The introduced data structure. called bit-map trie shows that we can implement a fast forwarding engine on the conventional Pentium processor by reducing the backbone routing table fits into Level 2 cache of Pentium II processor and shortens the searching path. Our experiments to evaluate the performance of proposed method show that this bit-map trie accomplishes 5.7 million lookups per second.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.43-48
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• 2008

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.

• Proceedings of the Korean Environmental Sciences Society Conference
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• 2020.10a
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• pp.217-217
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• 2020