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http://dx.doi.org/10.9708/jksci/2012.17.11.001

AMEX: Extending Addressing Mode of 16-bit Thumb Instruction Set Architecture  

Kim, Dae-Hwan (Dept. of Computer Information, Suwon Science College)
Abstract
In this paper, the extension of the addressing mode in the 16-bit Thumb instruction set architecture is proposed to improve the performance of 16-bit Thumb code. The key idea of the proposed approach is the introduction of new addressing modes for more frequent instructions by using the saved bits from the reduction of the register fields in less frequently used instructions. The proposed approach adopts efficient addressing modes from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To speed up access to a data list, scaled register offset addressing mode and post-indexed addressing mode are introduced for load and store instructions. Experiments show that the proposed approach improves performance by an average of 8.5% when compared to the conventional approach.
Keywords
Instruction set design; Addressing mode; Embedded processor; Thumb; ARM;
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Times Cited By KSCI : 2  (Citation Analysis)
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1 S. Segars, K. Clarke, and L. Goudge, "Embedded control problems, Thumb, andtheARM7TDMI," IEEE Micro, Vol. 15, No. 5, pp. 22-30, Oct. 1995.   DOI   ScienceOn
2 K. Kissell, "MIPS16: High-Density MIPS for the EmbeddedMarket", Technical report, Silicon Graphics MIPS Group, 1997.
3 Advanced RISC Machines Ltd., "ARM Annual Report & Accounts 2011," Advanced RISC Machines Ltd., 2011.
4 R. Phelan, "Improving ARM Code Density and Performance," Technical report, Advanced RISC Machines Ltd.. June 2003.
5 A. Krishnaswamy and R. Gupta, "Efficient Use of Invisible Registers in Thumb Code," In Proc. of the 38th IEEE/ACM International Symposiumon Microarchitecture, pp. 30-42, Nov 2005.
6 A. Krishnaswamy, and R. Gupta, "Dynamic coalescing for 16-bit instructions," ACM Transaction on Embedded Computing System, Vol. 4, No. 1, pp. 3-37, Feb. 2005.   DOI
7 J. H. Lee, S. M. Moon, andH.K. Choi, "Comparison of Bank Change Mechanisms for Banked Reduced Encoding Architectures," In Proc. of the International Conference on Computational Science and Engineering, Vancouver, Vol. 2, pp. 334-341, Aug. 2009.
8 Y. -J. Kwon, X.Ma, andH. J. Lee, "PARE: instruction set architecture for efficient code size reduction," IEE Electronics Letters, Vol. 35,No. 24, pp. 2098-2099,Nov. 1999.   DOI   ScienceOn
9 L. Dong, Z. Ji, G. Gui, and M. Hu, "Multithreading extension for Thumb ISA and decoder support," In Proc. of the 5th WSEAS Int. Conf. on Electronics, Hardware, Wireless and Optical Communications, pp. 78-81, 2006.
10 X.H. Xu, S. R. Jones, andC. T. Clarke, "ARM/THUMB code compression for embedded systems," In Proc. of 15th Int. Conf. on Microelectronics, pp. 32-35, 2003.
11 A.M. Fiskiran and R.B. Lee, "Performance Impact of Addressing Modes on Encryption Algorithms," In Proc. of the International Conference on Computer Design (ICCD 2001), pp. 542-545, Sep. 2001.
12 B. Li, and R. Gupta, "Bit Section Instruction Set Extension of ARMfor Embedded Applications," In Proc. of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pp. 69-78, Grenoble, France, 2002.
13 H.-J. Cheng, Y.-S. Hwang, R.-G. Chang, and C.-W. Chen, "Trading Conditional Execution for More Registers on ARMProcessors," In Proc. of the 8th IEEE/IFIP Int. Conf. on Embedded and Ubiquitous Computing (EUC), pp. 53-59, Dec. 2010.
14 H.-H. Chiang, H.-J. Cheng, and Y.-S. Hwang, "Doubling the Number of Registers on ARM Processors," In Proc. of the 16th Workshop on Interaction between Compilers and Computer Architectures (INTERACT-16), Feb. 2012.
15 S. Bartolini, I. Branovic, R. Giorgi, andE.Martinelli, "A Performance Evaluation of ARMISA Extension for Elliptic Curve Cryptography over Binary Finite Fields," In Proc. of 16th Symposiumon Computer Architecture and High Performance Computing, pp.238-245, 2004.
16 Hedley Francis, "ARMDSP-Enhanced Extensions," ARM Ltd., 2001.
17 ARM Ltd. "ARM Jazelle Technology", 2001.
18 J. Rokov, and D. Ing, "ARM Architecture and Multimedia Applications," RIZ-Transmitters Co., 2010.
19 ARMLtd. "Introducing NEONTM Development Article," 2009.
20 J. Goodacre, andA. N. Sloss, "Parallelism and the ARM instruction set architecture," Computer, Vol. 38, No. 7, pp. 42-50, 2005.   DOI
21 S. -M. Kang, and J. -M. Kim, "Multimedia Extension Instructions and Optimal Many-core Processor Architecture Exploration for Portable Ultrasonic Image Processing," Journal of The Korea Society of Computer and Information, Vol. 17, No. 8, pp. 1-10, 2012.   과학기술학회마을   DOI   ScienceOn
22 A. Krishnaswamy, and R. Gupta, "Profile guided selection of armand thumb instructions," In Proc. of the ACM SIGPLAN Joint Conf. on Languages Compilers and Tools for Embedded Systems & Software and Compilers for Embedded Systems, pp. 55-64, 2002.
23 Y. -B. Jung, Y. -M. Kim, C. -H. Kim, and J. -M. Kim, "Performance Evaluation and Verification of MMX-type Instructions on an Embedded Parallel Processor," Journal of The Korea Society of Computer and Information, Vol. 16, No. 10, pp. 11-21, 2011.   과학기술학회마을   DOI   ScienceOn
24 J. Lee, J. Kim, C. Jang, S. Kim, B. Egger, K. Kim, and S. Han, "FaCSim: A Fast and Cycle-Accurate Architecture Simulator for Embedded Systems," In Proc. of the Int. Conf. on Languages, Compilers, and Tools for Embedded Systems (LCTES'08), Tucson, Arizona, USA, pp. 89-100, June 2007.