• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.339-344
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• 2014

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) $0.18{\mu}m$. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately $1.6{\Omega}$. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.351-354
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• 2004

This thesis presents Bipolar transistor with SAVEN(Self-Aligned VErtical Nitride) structure as a high-speed device which is essential for high-speed system such as optical storage system or mobile communication system, and proposes 0.8${\mu}m$ BiCMOS Process which integrates LDD nMOS, LDD pMOS and SAVEN bipolar transistor into one-chip. The SPICE parameters of LDD nMOS, LDD pMOS and SAVEN Bipolar transistor are extracted, and comparator operating at 500MHz sampling frequency is designed with them. The small Parasitic capacitances of SAVEN bipolar transistor have a direct effect on decreasing recovery time and regeneration time, which is helpful to improve the speed of the comparator. Therefore the SAVEN bipolar transistor with high cutoff frequency is expected to be used in high-speed system.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.1-8
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• 2003

In this study, the high performance BCD device structure which satisfies the high voltage and fast switching speed characteristics is devised. Through the process and device simulation, optimal process spec. & device spec. are designed. We adapt double buried layer structure, trench isolation process, n-/p-drift region formation and shallow junction technology to optimize an electrical property as mentioned above. This I.C consists of 20V level high voltage bipolar npn/pnp device, 60V level LDMOS device, a few Ampere level VDMOS, 20V level CMOS device and 5V level logic CMOS.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1460-1462
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• 1994

BiCMOS is the newly developed technology that integrates both CMOS and bipolar structures on the same integrated circuit. Improved performance can be obtained from combining the advantages of high density and low power in CMOS with the speed and current capibility advantages by bipolar. However, the major drawbacks to BiCMOS are high cost, long fabrication time and difficulty of merging CMOS with bipolar without degrading of device Performance because CMOS and bipolar share same process step. In this paper, N-Well CMOS oriented BiCMOS process and optimization of device performance are studied when N-Well links CMOS with bipolar process step by 2D process and 3D Device simulation. From the simulation, Constriction of linking process step has been understood and provided to give the method of choosing BiCMOS for various analog design request.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.20-26
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• 1993

The base-collector capacitance of an npn bipolar transistor in bipolar or BiCMOS technology has significant influence on the switching performances, and comprises pnjunction component and MOS component. Both components have complicated dependences on the isolation oxide structure, epitaxial doping density, and bias voltage. Analytical/empirical formulas for both components are derived in this paper for a generic isolation structure as a function of epitaxial doping density and bias voltage based on some theoretical understanding and two-dimensional device simulations. These formulas are useful in estimating the effect of device isoation schemes on the switching speed of bipolar transistors.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.249-252
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• 2000

A new Smart rower IC's based on the Partial SOI technology was designed for such applications as mobile communication systems, high-speed HDD systems etc. A new methodology of integrating a 0.8${\mu}{\textrm}{m}$ BiCMOS compatible Smart Power technology, high voltage bipolar device, high speed SAVEN bipolar device, LDD NMOSFET and a new LDMOSFET based on the Partial SOI technology is presented in this paper. The high voltage bipolar device has a breakdown voltage of 40V for the output stage of analog circuit. The optimized Partial SOI LDMOSFET has an off-state breakdown voltage of 75 V and a specific on- resistance of 0.249mΩ.$\textrm{cm}^2$ with the drift region length of 3.5${\mu}{\textrm}{m}$. The high-speed SAVEN bipolar device shows cut-off frequency of about 21㎓. The simulator DIOS and DESSIS has been used to get these results.

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.131-135
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• 2009

This paper reviews the characteristics of Power MOSFET device technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits.

• Proceedings of the KOR-BRONCHOESO Conference
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• 1978.06a
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• pp.9.1-10
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• 1978

Recently the authors have observed various wave-forms by insertion of induction coil into the scala tympani as well as attached outer device in the outside of the body in damaged hair cells of the cats. In the cochlear nerve. action potential indicated different polarities induced by examination of the bundle of the cochlear nerve fibers. Impulse wave-form as a result of excitation of cohlear nerve fibers showed bipolar wave-form such as negative 1 and positive 1. Therefore action potential showed also bipolar wave-form as above mentioned. We can obtained suitable response with above mentioned outer and inner device as an exact oscillogram.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.292-295
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• 2004

The SIT was introduced by Nishizawa. in 1972. When compared with high-voltage, power bipolar junction transistors, SITs have several advantages as power switching devices. They have a higher input impedance than do bipolar transistors and a negative temperature coefficient for the drain current that prevents thermal runaway, thus allowing the coupling of many devices in parallel to increase the current handling capability. Furthermore, the SIT is majority carrier device with a higher inherent switching speed because of the absence of minority carrier recombination, which limits the speed of bipolar transistors. This also eliminates the stringent lifetime control requirements that are essential during the fabrication of high-speed bipolar transistors. This results in a much larger safe operating area(SOA) in comparison to bipolar transistors. In this paper, vertical SIT structures are proposed to improve their electrical characteristics including the blocking voltage. Besides, the two dimensional numerical simulations were carried out using ISE-TCAD to verify the validity of the device and examine the electrical characteristics. A trench gate region oxide power SIT device is proposed to improve forward blocking characteristics. The proposed devices have superior electrical characteristics when compared to conventional device. Consequently, the fabrication of trench oxide power SIT with superior stability and electrical characteristics is simplified.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.10
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• pp.821-829
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• 1991

In this paper, a BICMOS technology that has CMOS devices for digital application and bipolar devices for high voltage (80V) analog applications is presented. Basic concept to design BICMOS device is simple process technology without making too many performance trade-offs. The base line process is poly gate p-well CMOS process and three additional masking steps are added to improve bipolar characteristics. The key ingredients of bipolar integration are n+ buried layer process, up/down isolation process and p-well base process. The bipolar base region is formed simultaneously with the region of CMOS p-well area to reduce mask and heat cycle steps. As a result, hFE value of NPN bipolar transistor is 100-150(Ic=1mA). Collector resistance value is 138 ohm in case of bent type collector structure. Breakdown voltage of BVebo, BVcbo and BVceo are 21V, 115V and78V respectively. Threshold voltage is ${\pm}$1.0V for NMOS and PMOS transistor. Breakdown voltage of NMOS and PMOS transistor is obtained 22V and 19V respectively. 41 stage CMOS ring oscillator has 0.8ns delay time.