• Smart Structures and Systems
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• v.8 no.1
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• pp.119-137
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• 2011

A bio-inspired two-mode structural health monitoring (SHM) system based on the Na$\ddot{i}$ve Bayes (NB) classification method is discussed in this paper. To implement the molecular biology based Deoxyribonucleic acid (DNA) array concept in structural health monitoring, which has been demonstrated to be superior in disease detection, two types of array expression data have been proposed for the development of the SHM algorithm. For the micro-vibration mode, a two-tier auto-regression with exogenous (AR-ARX) process is used to extract the expression array from the recorded structural time history while an ARX process is applied for the analysis of the earthquake mode. The health condition of the structure is then determined using the NB classification method. In addition, the union concept in probability is used to improve the accuracy of the system. To verify the performance and reliability of the SHM algorithm, a downscaled eight-storey steel building located at the shaking table of the National Center for Research on Earthquake Engineering (NCREE) was used as the benchmark structure. The structural response from different damage levels and locations was collected and incorporated in the database to aid the structural health monitoring process. Preliminary verification has demonstrated that the structure health condition can be precisely detected by the proposed algorithm. To implement the developed SHM system in a practical application, a SHM prototype consisting of the input sensing module, the transmission module, and the SHM platform was developed. The vibration data were first measured by the deployed sensor, and subsequently the SHM mode corresponding to the desired excitation is chosen automatically to quickly evaluate the health condition of the structure. Test results from the ambient vibration and shaking table test showed that the condition and location of the benchmark structure damage can be successfully detected by the proposed SHM prototype system, and the information is instantaneously transmitted to a remote server to facilitate real-time monitoring. Implementing the bio-inspired two-mode SHM practically has been successfully demonstrated.

• Journal of Korea Multimedia Society
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• v.6 no.3
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• pp.508-517
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• 2003

This paper presents perceptual model with a stochastic multiresolution characteristic that can be applied with watermark embedding in the biorthogonal wavelet domain. The perceptual model with adaptive watermarking algorithm embeds at the texture and edge region for more strongly embedded watermark by the SSQ. The watermark embedding is based on the computation of a NVF that has local image properties. This method uses non- stationary Gaussian and stationary Generalized Gaussian models because watermark has noise properties. The particularities of embedding in the stationary GG model use shape parameter and variance of each subband regions in multiresolution. To estimate the shape parameter, we use a moment matching method. Non-stationary Gaussian model uses the local mean and variance of each subband. The experiment results of simulation were found to be excellent invisibility and robustness. Experiments of such distortion are executed by Stirmark 3.1 benchmark test.

• ETRI Journal
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• v.30 no.3
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.87-95
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• 2004

This paper proposes a new test data compression/decompression method for SoC(Systems-on-a-Chip). The method is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed method is based on Modified Statistical Coding (MSC) and Input Reduction (IR) scheme, as well as a novel mapping and reordering algorithm proposed in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.93-100
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• 2008

In this paper, we address a novel simulated annealing(SA)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip(SoCs), on the assumption that the test platform proposed in [1] is installed. The proposed method efficiently mixed the rectangle packing method with SA and improved the scheduling results by locally changing the test access mechanism(TAM) widths for cores and the testing orders. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce the overall test time.

• English Language & Literature Teaching
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• v.12 no.1
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• pp.221-238
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• 2006

This study investigates the reliability of plagiarism measurement in the ESL essay writing context. The current study aims to address the answers to the following research questions: 1) How does plagiarism measurement affect test reliability in a psychometric view? and 2) how do raters conceive the plagiarism in their analytic scoring? This study uses the mixed-methodology that crosses quantitative-qualitative techniques. Thirty eight international students took an ESL placement writing test offered by the University of Illinois. Two native expert raters rated students' essays in terms of 5 analytic features (organization, content, language use, source use, plagiarism) and made a holistic score using a scoring benchmark. For research question 1, the current study, using G-theory and Multi-facet Rasch model, found that plagiarism measurement threatened test reliability. For research question 2, two native raters and one non-native rater in their email correspondences responded that plagiarism was not a valid analytic area to be measured in a large-scale writing test. They viewed the plagiarism as a difficult measurement are. In conclusion, this study proposes that a systematic training program for avoiding plagiarism should be given to students. In addition, this study suggested that plagiarism is measured reliably in the small-scale classroom test.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.72-84
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• 2000

The test patterns for path delay faults consist of two patterns. So in order to test the delay faults, a new weight generation algorithm that is different from the weight generation algorithm for stuck-at faults must be applied. When deterministic test patterns for weight calculation are used, the deterministic test patterns must be divided into several subsets, so that Hamming distances between patterns are not too long. But this method makes the number of weight sets too large in delay testing, and may generate inaccurate weights. In this pater, we perform fault simulation without pattern partition. Experimental results for ISCAS 89 benchmark circuits prove the effectiveness of the new weight generation algorithm proposed in this paper.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.1-16
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• 1999

Critical is used frequently in many test generation procedures. In this paper, the critical-pair is defined as a extended concept of critical. Also, the criticality, the critical rate, the critical number, and the critical setting rate are defined which represent the characteristics of critical. In these elements, it is proved that the usage of the critical-pair is more efficient than that of the single critical. in FFR, it is also showed that the critical-pair is more efficient in evaluation number of critical values when the test pattern is generated, in the number of searching lines, and the test generation time. The experimental results of the critical-pair on the ISCAS85 benchmark test circuits are compared and analyzed to the single critical using simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.1
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• pp.235-244
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• 1999

This Paper proposes a new compaction algorithm for IDDQ testing in CMOS Circuits. A primary test pattern is generated by the primitive fault pattern which is able to detect GOS(gate-oxide short) and the bridging faults in an internal primitive gate. The new algorithm can reduce the number of the test vectors by decreasing the don't care(X) in the primary test pattern. The controllability of random number is used on processing of the backtrace together four ones of heuristics. The simulation results for the ISCAS-85 benchmark circuits show that the test vector reduction is more than 45% for the large circuits on the average compared to static compaction algorithms.

• Journal of Information Processing Systems
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• v.13 no.5
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• pp.1089-1102
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• 2017

In software systems, it has been observed that a fault is often caused by an interaction between a small number of input parameters. Even for moderately sized software systems, exhaustive testing is practically impossible to achieve. This is either due to time or cost constraints. Combinatorial (t-way) testing provides a technique to select a subset of exhaustive test cases covering all of the t-way interactions, without much of a loss to the fault detection capability. In this paper, an approach is proposed to generate 2-way (pairwise) test sets using genetic algorithms. The performance of the algorithm is improved by creating an initial solution using the overlap coefficient (a similarity matrix). Two mutation strategies have also been modified to improve their efficiency. Furthermore, the mutation operator is improved by using a combination of three mutation strategies. A comparative survey of the techniques to generate t-way test sets using genetic algorithms was also conducted. It has been shown experimentally that the proposed approach generates faster results by achieving higher percentage coverage in a fewer number of generations. Additionally, the size of the mixed covering arrays was reduced in one of the six benchmark problems examined.