• Transactions on Electrical and Electronic Materials
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• v.9 no.1
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.767-769
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• 2002

A novel RE configurable device composed by bare-chip, bumps and board are proposed. We call this "Field-Programmable RF Gate Array (FPRA)," This device, a kind of programmable system packages, has a potential to be applied to wireless communication terminals such as software-defined radio.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.183-192
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• 2001

1- Buildup PCB technology is utilized to a bare chip attach substrate technology for packaging of semiconductor chip 2- Requirement for the substrate design rule is described in SIA International Technology Roadmap for Semiconductor. 3- There are seven fabrication methods of build-up technology. 4- Coating and lamination for resin and photo, and laser for micro via hope processes are available. Below $50\mu\textrm{m}$ in diameter is possible. 5- Fine pitch lines down to $30\mu\textrm{m}$ can be achieved by pattern plating with better electrical property. 6- Dielectric loss reduction is a key material improvement item for next generation build-up technology. 7- High band width up to 512 GB/s is possible with current wiring groundrule.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.59-63
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• 2013

In this paper, the impact of the copper densities of substrate layers on IC package warpage is studied experimentally and numerically. The substrate strips used in this study contained two metal layers, with the metal densities and patterns of these two layers varied to determine their impacts. Eight legs of substrate strips were prepared. Leg 1 to leg 5 were prepared with a HD (high density) type of strip and leg 6 to leg 8 were prepared with UHD (ultra high density) type of strip. The top copper metal layer was designed to feature meshed patterns and the bottom copper layer was designed to feature circular patterns. In order to consider the process factors, the warpage of the substrate bottom was measured step by step with the following manufacturing process: (a) bare substrate, (b) die attach, (c) applying mold compound (d) and post reflow. Furthermore, after the post reflow step, the substrate strips were diced to obtain unit packages and the warpage of the unit packages was measured to check the warpage trends and differences. The experimental results showed that the warpage trend is related to the copper densities. In addition to the experiments, a Finite Element Modeling (FEM) was used to simulate the warpage. The nonlinear material properties of mold compound, die attach, solder mask, and substrate core were included in the simulation. Through experiment and simulation, some observations were concluded.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1081-1090
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• 2013

In this paper, a C-band 10 W power amplifier with internally matched input and output matching circuit is designed and fabricated. The used power transistor for the power amplifier is GaAs pHEMT bare-chip. The wire bonding analysis considering the size of the capacitor and the position of transistor pad improves the accurate design. The matching circuit design with the package effect using EM simulation is performed. To reduce the unsymmetry of IMD3 in 2-tone measurement due to the memory effect, the bias circuit minimizing the memory effect is proposed and employed. The measured $P_{1dB}$, power gain, and power added efficiency are 39.8~40.4 dBm, 9.7~10.4 dB, and 33.4~38.0 %, respectively. Adopting the proposed bias circuit, the difference between the upper and lower IMD3 is less than 0.76 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1239-1247
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• 2012

In this paper, design and fabrication of solid state power amplifier(SSPA) using GaN HEMT chip for X-band frequency are presented. The SSPA consists of the power supply for stable power and the control unit for communication and controlling the internal module, the RF Part to amplify RF signal, In particular the adopted active device for the RF Parts is GaN HEMT Bare chip of TriQuint company, the RF parts consists of pre-stage, drive-stage, main power-stage and each amplifier is designed with input and out matching circuit. The developed power amplifier demonstrated more than 300 W peak output power in condition of 26 % duty, max. pulse width 100us for the X-band frequency( 500 MHz bandwidth) and can apply to marine radar systems.

• Bulletin of the Korean Chemical Society
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• v.33 no.4
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• pp.1135-1140
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• 2012

An electrochromatographic microchip with carboxyl-group-derivatized mono-disperse silica packing was prepared from the corresponding colloidal silica solution by utilizing capillary action and self-assembly behavior. The silica beads in water were primed by the capillary action toward the ends of cross-patterned microchannel on a cyclic olefinic copolymer (COC) substrate. Slow evaporation of water at the front of packing promoted the self-assembled packing of the beads. After thermally binding a cover plate on the chip substrate, reservoirs for sample solutions were fabricated at the ends of the microchannel. The packing at the entrances of the microchannel was silver coated to fix utilizing an electroless silver-plating technique to prevent the erosion of the packed structure caused by the sudden switching of a high voltage DC power source. The electrochromatographic behavior of the microchip was explored and compared to that of the microchip with bare silica packing in basic borate buffer. Electrophoretic migration of Rhodamine B was dominant in the microchip with the carboxyl-derivatized silica packing that resulted in a migration approximated twice as fast, while the reversible adsorption was dominant in the bare silica-packed microchip. Not only the faster migration rates of the negatively charged FITC-derivatives of amino acids but also the different migration due to the charge interaction at the packing surface were observed. The electrochromatographic characteristics were studied in detail and compared with those of the bare silica packed microchip in terms of the packing material, the separation potential, pH of the running buffer, and also the separation channel length.

• Transactions on Electrical and Electronic Materials
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• v.4 no.2
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• pp.10-14
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• 2003

Flexible displays such as plastic-based liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDDs) have been researched and developed at KETI since 1997. The plastic film substrate is very weak to heat and pressure compared to glass substrate, that its fabrication process is limited to 110$^{\circ}C$ and low pressure. The ITO films were deposited on the bare plastic film substrate by rf-magnetron sputtering. Moreover, in order to maintain uniform cell gap and pressure on the plastic film substrate, we utilized newly-invented jig and fabrication process. Electro-optical characteristics were better than or equivalent to those of typical glass LCDs though it is thinner, lighter-weight, and more robust than glass LCDs.

• Journal of the Microelectronics and Packaging Society
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• v.2 no.1
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• pp.59-68
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• 1995

박막제조 기술 및 BGA패캐지를 이용하여 Wellcom 2000 system 소요 OCU Board 의 집적화를 구현하였다. 기존 PCB에 실장되는 소자 일부를 2 Channel BGA 패캐지로 모 듈화한 결과 약 1/6로 소형화시킬수 있었으며 8 Channel의 모율화는 현재 진행중인 다층 구조의 제조 기술 개발과 아울러 BGA 패캐지로 실현이 가능하며 1/10로집접화할수 있음을 알수 있었다. 또한 PCB위에 Bare Chip을 실장하여 Wire Bonding 한 COB를 구현하여 CBGGA의 PCB실장과 함께한 모듈을 형성해 보았다. CBGA패캐지에 Ball Shear Test, In Circuit Test 온도 환경주기시험(TCT) 진동시험을 통하여 신뢰성을 입증하였다. 이때 CBGA의 Coplanarity(3.2%) 증진을 위하여 Ceramic Pad에 선택적인 도금 방식을 개발적용 하였다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.