• Journal of Korean Society of Transportation
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• v.26 no.6
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• pp.61-70
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• 2008

The study proposed a new type of bus information, Real-time Bus Crowdedness (RBC) information, to meet various demands of users and improve the convenience level of using public transportation, while existing bus information provided by bus information systems(BIS) were limited to bus operating information such as predicted bus arrival time. To analyze the impacts of providing the proposed RBC information, stated preference(SP) survey was performed and a methodology of disaggregate analysis (e.g., binary logit) was applied to develop passenger choice models. Additionally, passenger choice models incorporating the heterogeneity of different user groups(i.e., by age or trip purposes) were developed to evaluate the different responses on RBC information. The results showed that providing RBC information was significantly related to users' bus choices and the responses of user groups were significantly different, especially the age group of more then 60 was most affected by the RBC information on their bus choices. Also trip purposes were significantly related to users' bus choices, for instance the impacts of providing RBC information was bigger for non-business trips(leisure/meet friend/personal business, shopping, hospital) compared to business trip.

• Journal of the Ergonomics Society of Korea
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• v.36 no.2
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• pp.69-86
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• 2017

Objective: The present study is intended to develop an improved bus seat armrest design by evaluating various bus armrest designs from ergonomic aspects. Background: An ergonomic armrest design which considers the sitting postures and body shapes of passengers can improve the convenience and comfort of a bus seat. Method: Subjective satisfaction of each of five design dimensions (length, width, height from seatpan, shape, and angle) was evaluated for seven bus seat armrest designs in various sizes and shapes by 58 participants (28 males and 33 females) using a 7-point scale (1: very dissatisfied, 4: neutral, and 7: very satisfied). Improved bus seat armrest designs adjustable in length and rotatable to the left or right (sliding and rotating armrest, SRA) with a concave, flat, or convex shape of the upper part were developed by considering the preferred design features and the body size and shape in sitting posture and needs of passengers and then compared with a conventional armrest. Results: A bus seat armrest with a wide width (40~50mm), a long length (360mm), a lower height (213mm), and a curved shape was found significantly preferred in terms of comfort. The proposed armrest designs (SRA-convex, SRA-flat, and SRA-concave) improved satisfaction by 46~62% for length suitability, 184~216% for width suitability, 205~214% for angle suitability, 138~181% for contact area suitability, and 49~64% for height suitability, 138~174% for comfort, and 93~111% for overall satisfaction. Conclusion: The preferred design features and passengers' needs of bus seat armrest were identified and the SRA designs were recommended for better usability. Application: The ergonomic design process of bus seat armrest employed in the present study can be applied to designing armrests in various vehicles for better convenience and comfort.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.9-18
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• 2005

This paper proposes the novel synchronous segmented bus architecture that has the pipeline bus architecture based on OCP(open core protocol) and the memory-oriented bus for MPEG system. The proposed architecture has bus architectures that support the memory interface for image data processing of MPEG system. Also it has the segmented hi-directional multiple bus architecture for multitasking processing by using multi -masters/multi - slave. In the scheme address of masters and slaves are fixed so that they are arranged for the location of IP cores according to operational characteristics of the system for efficient data processing. Also the bus architecture adopts synchronous segmented bus architecture for reuse of IP's and architecture or developed chips. This feature is suitable to the high performance and low power multimedia SoC systum by inherent characteristics of multitasking operation and segmented bus. Proposed bus architecture can have up to 3.7 times improvement in the effective bandwidth md up to 4 times reduction in the communication latency.

• Transactions of the Korean Society of Automotive Engineers
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• v.24 no.2
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• pp.198-204
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• 2016

In this study, a wind tunnel test was conducted to measure the aerodynamic characteristics of a streamline-designed high-speed bus with the change of wind direction and speed and the result is compared with the aerodynamic performance of a commercialized high-speed bus model (Model-0) manufactured by Zyle Daewoo Bus Corp. Aerodynamic performance of the existing rear-spoiler was tested to prove its aerodynamic effect on the test model bus. From the study, it was found that 24.6 % of the total drag of the original bus model (Model-0) was reduced on the streamline-designed model bus(model-1) without the rear-spoiler but only 14.3 % of the total drag was reduced with the spoiler on the streamlined model bus. It means that the rear spoiler does not work properly with the streamlined model bus (model-1) and should be noted that an optimum design of a rear-spoiler of a vehicle is important to reduce the induced pressure drag and increase the driving stability of a vehicle against yaw motion. The experimental outcome was also compared to the previous numerical research result to evaluate the reliability of the numerical algorithm of the aerodynamic performance analysis of a vehicle. The error rate (%) of the numerical result to the experimental output is about 5.4 % and it is due to the simplified body configuration of the numerical model bus. The drag increases at the higher yaw angle because the transparent frontal area of the model vehicle increases and the downward force increases with the yaw angle as well. It has a positive effect to the driving stability of the vehicle but the moderated downward force should be kept for the fuel economy of a vehicle.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2078-2082
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• 2010

The general bus system architecture consists of masters, slaves, arbiter, decoder and so on in shared bus. As several masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, The efficiency of bus usage can be determined. Fixed Priority, Round-Robin, TDMA, Lottery arbitration are studied in conventional arbitration method. Conventional arbitration method is considered bus priority primarily, actual bus utilization didn't considered. In this paper, we propose arbitration method using bus utilization operating block of each master, we verify the performance compared with the other arbitration methods through throughput performance. From the result of performance verification, we confirm that proposed arbitration method, matched bus utilization set by the user 40%, 20%, 20%, 20%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.38-44
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• 2009

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method bus system performance can be charged definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this stuff, we proposed the score arbitration method and composed TLM algorithm. Also we analyze the performance compared with general arbitration methods through simulation. In the future, bus arbitration policy will be developed with the basis of the score arbitration method and improve the performance of bus system.

• Journal of the Korean Society of Safety
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• v.33 no.1
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• pp.109-117
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• 2018

This study examined the effect of Behavior Based Safety(BBS) program on safe behaviors of bus drivers and passengers. Four male bus drivers working at a H transportation company situated in Seoul participated in this study. BBS program consisted of education, prompts, and self-monitoring with goal setting. Dependent variables were the percentage of two safe driving behaviors of bus drivers (departure after stopping for 3 seconds, announcement for holding bus handles) and the percentage of one safe behavior of passengers getting on the busses those drivers drove (holding bus handles). A primary observer and two trained assistant observers measured two safe behaviors of the bus drivers with behavior checklists by riding on the busses and the passengers' safe behavior was observed by CCTV installed on each bus. An ABC multiple baseline design across participants was adopted. After baseline(A), education and prompts(B) and self-monitoring with goal setting(C) were introduced sequentially to each participant. The results showed that BBS program was effective to increase both bus drivers' and passengers' safe behaviors. Especially self-monitoring with goal setting was more effective in improving safe behaviors of bus drivers than education/prompts. These results suggest that education/prompts and self-monitoring with goal setting would be an alternative treatment technique to improve safety for lone workers such as bus drivers.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.6
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• pp.324-332
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• 2005

In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

• Journal of Korean Society of Transportation
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• v.29 no.5
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• pp.43-54
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• 2011

After implementing "Semi-public management system of intra-city bus", the burden of financial aid for unprofitable routes is on the increase in Busan metro city. It becomes a heavy burden on the local finance, which needs to be resolved for improving the intra-bus system. The rainfall is one of the factors influencing the demands for intra-bus in urban transportation. Motivated by this fact, this study investigates the impact of rainfall on the intra-city bus demand. Actual bus users are surveyed on their patterns and recognition of using the bus according to the amount of rainfall. A rainfall forecast model using ordered probit model is presented, and the elasticity of the intra-city bus utilization to the amount of rainfall is also analyzed. The resulting findings could be applied to promote the use of intra-city buses and also be utilized as basic data for other studies to improve the intra-city bus system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.885-888
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• 2015

A secure and effective on-chip bus for detecting and preventing malicious attacks by infected IPs is presented in this paper. Most system inter-connect (on-chip bus) are vulnerable to hardware Trojan (Malware) attack because all data and control signals are routed. A proposed secure bus with modifications in arbitration, address decoding, and wrapping for bus master and slaves is designed using the Advanced High-Performance and Advance Peripheral Bus (AHB and APB Bus). It is implemented with the concept that arbiter checks share of masters and manage infected masters and slaves in every transaction. The proposed hardware is designed with the Xilinx 14.7 ISE and verified using the HBE-SoC-IPD test board equipped with Virtex4 XC4VLX80 FPGA device. The design has a total gate count of 40K at an operating frequency of 250MHz using the $0.13{\mu}m$ TSMC process.