• ETRI Journal
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• v.26 no.6
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1992.04b
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• pp.605-614
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• 1992

초기단계의 제품 검사방법은 단순히 제품이 제대로의 기능을 수행하는지 안하는지에 대해서만 검사하고 결정을 내릴 뿐이었다. 대부분의 검사란, 검사자에게 최종적으로 제품이 인수된 후에 제품의 상태여부를 한정적이고, 제한적으로만 판단하여 검사결과를 제공하여왔다. 현대의 제품특성이 구조적 복잡성의 증가, 제품불량 현상파악의 난이도 증가등으로 제품의 사용절차, 검사, 유지보수, 부품교환등이 점점 더 난해해지고, 검사자의 개인적인 숙련도도 증가하게 되어, 제품을 유지보수하는데 더 많은 비용과 시간을 필요로하게 되었다. 이러한 문제들의 해결방안의 하나로 제품의 자체에 스스로 검사할 수 있는 체계적인 시스템을 설치하게 되어 BIT(Built-In-Test)가 탄생하게 되었다. BIT는 현존하는 제품뿐만아니라, 생산될 제품의 설계단계에서도 많이 응용되어 제품의 RAM(Reliability, Availability, Maintainability)에 많은 기여를 해왔다. 이 PAPER는 지금까지 BIT가 주로 Military System에 적용되어온 것을 Commercial system으로의 변환을 위한 기초작업을 제시하고 여러 대안을 열거하였으며, BIT가 갖고 있는 문제점들을 파악하여, 향후 고도화 되가는 산업사회의 요구에 부응할 수 있는 토대를 마련코자 Survey하였다.

• Journal of KIISE:Software and Applications
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• v.29 no.1_2
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• pp.65-79
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• 2002

Object-oriented frameworks need to be systematically tested because they are reused in developing many applications software. They also need additional testing whenever they are extended for reuse. Frameworks, however, have properties that make it difficult to control and observe the testing of the parts that were modified and extended. In this paper, we describe the method of embedding test components as BIT(Built-In Test) into the framework's hot spots in order to efficiently detect the faults through testing that occurred while implementing application programs by modifying and extending the framework. The test components embedded into a framework make it easy to control and observe testing the framework, and thereby improve the testability of frameworks. Test components designed by the method proposed in this paper can be dynamically attached and detached to/from hot spots of a framework without changes or intervention to the framework code.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.59-70
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• 1993

An efficient test method based on march test is presented to cover line leakage failures associated with bit and word lines or mega bit DRAM chips. A modified column march (Y-march) pattern is derived to improve fault coverage against the data retention failure. Time delay concept is introduced to develop a new column march test algorithm detecting various data retention failures. A built-in test circuit based on the column march pattern is designed and verified using logic simulation, confirming correct test operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.43-48
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• 2008

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.383-386
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• 2017

Avionics, a type of embedded system, requires high safety and reliability. Failure of avionics equipment can have a significant impact on aircraft operations and, in the worst case, could result in loss of life for pilots and passengers. In this paper, we propose a Built-In-Test (hereafter referred to as BIT) design technique that can detect possible faults in avionics equipments in order to increase the reliability of avionics system and a design that can improve the Mean Time Between Failure (hereafter: MTBF) and applied it to real aviation electronic equipment to improve reliability.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.226-233
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• 2012

In this paper, we propose a 'linear approximation method' which is an accelerated BER (Bit Error Rate) test method for high speed interfaces, based on an analytical BER model. Both the conventional 'Q-factor estimation method' and 'linear approximation method' can predict a timing margin for $10^{-13}$ BER with an error of about 0.03UI. This linear approximation method is implemented on a hardware as an accelerated Built-In Self Test (BIST) with an internal BERT (BET Tester). While a direct measurement of a timing margin in a 3Gbps interface takes about 5.6 hours with $10^{-13}$ BER requirement and 95% confidence level, the accelerated BIST estimates a timing margin within 0.6 second without a considerable loss of accuracy. The test results show that the error between the estimated timing margin and the timing margin from an actual measurement using the internal BERT is less than 0.045UI.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.5
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• pp.599-604
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• 2018

For missile systems, sustaining high reliability and ensuring economical maintenance are very important. In the Republic of Korea, for most missiles, periodic inspection is mandatory for missiles in the field. Every fixed number of years, they are returned to the ordnance depot to be tested and repaired if faults are found. Almost all missiles have a built-in test (BIT) capability. With the BIT, faulty missiles can be isolated anytime during operations or storage in the launchers. So the reliability and the maintenance costs of the missiles greatly depend on the length of the inspection cycle and the BIT/inspection quality. In this paper, we suggest a model for predicting the storage reliability of missiles subjected to non-periodic tests and periodic inspections, excluding overlapping failures. Some numerical examples are given. This model will be useful for determining the length of the periodic inspection cycle.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.27-34
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• 2006

During Built-In Self-Test(BIST), The set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault. In order to reduce the test time, we can remove useless patterns or change from them to useful patterns. In this paper, we reseed modify the pseudo-random and use an additional bit flag to improve test length and achieve high fault coverage. the fat that a random tset set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we choose number of different less bit, leading to very short test length. the technique we present is applicable for single-stuck-at faults. the seeds we use are deterministic so 100% faults coverage can be achieve.