• Journal of the Korea Convergence Society
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• v.8 no.11
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• pp.15-20
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• 2017

Recently, with the development of the IT industry, interest in computer convergence technology is increasing in various fields. Especially, in the semiconductor field, a vision system that uses a camera and computer convergence is often used to inspect semiconductor device defects in the production process. Various systems have been studied to remove noise, which is a major cause of degradation in processing of data related to these image processing systems. In this paper, we try to detect defects in BGA (Ball Grid Array) package devices by recognizing defects in advance during mass production. We propose a measurement system using a Gaussian filter, a Median filter, and an Average filter, which are widely used for noise reduction of image data Applying the proposed system to the manufacturing process of the BGA package can be used to judge whether the defect is good or not, and it is expected that productivity will be improved.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.126-130
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• 2021

The ball grid array is one of the packaging methods that used in high density printed circuit board. Solder void defects caused by voids in the solder ball during the BGA process do not directly affect the reliability of the product, but it may accelerate the aging of the device on the PCB layer or interface surface depending on its size or location. Void inspection is important because it is related in yields with products. The most important process in the optical inspection of solder void is the segmentation process of solder and void. However, there are several segmentation algorithms for the vision inspection, it is impossible to inspect all of images ideally. When X-Ray images with poor contrast and high level of noise become difficult to perform image processing for vision inspection in terms of software programming. This paper suggests the solution to deal with the suggested problem by means of using Mask R-CNN instead of digital image processing algorithm. Mask R-CNN model can be trained with images pre-processed to increase contrast or alleviate noises. With this process, it provides more efficient system about complex object segmentation than conventional system.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.45-52
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• 2011

It is known that test methods to evaluate solder joint reliability are die shock test, die shear test, 3points bending test, and thermal shock test. The present study investigated the effects of failure mode on 3 types (as-reflowed, $85^{\circ}C$/85%RH treatment, and $150^{\circ}C$/10hr aging) of solder joints for flip-chip BGA package by using various test methods. The test methods and configurations are reported in detail, i.e. die shock, die shear, 3points bending, and thermal shock test. We focus on the failure mode of solder joints under various tests. The test results indicate that die shock and die shear test method can reveal brittle fracture in flip-chip ball grid array (FCBGA) packages with higher sensitivity.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.233-241
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces strictly related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2004.09a
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• pp.211-219
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• 2004

A new alloy definition will be presented concerning increasing demands for the board level reliability of miniaturized interconnections. The damage mechanism for LFBGA components on different board finishes is not quite understood. Further demands from mobile phones are the drop test, characterizing interface performance of different package constructions in relation to decreased pad constructions and therefore interfaces. The paper discusses the characterization of interfaces based on SnPb, SnPbXYZ, SnAgCu and SnAgCuInNd ball materials and SnAgCuInNd as solder paste, the stability after accelerated tests and the description of modified interfaces stric시y related to the assembly conditions, dissolution behavior of finishes on board side and the influence of intermetallic formation. The type of intermetallic as well as the quantity of intermetallics are observed, primaliry the hardness, E modules describing the ability of strain/stress compensation. First results of board level reliability are presented after TCT-40/+150. Improvement steps from the ball formulation will be discussed in conjunction to the implementation of lead free materials. In order to optimize ball materials for area array devices accelareted aging conditions like TCTs were used to analyze the board level reliability of different ball materials for BGA, LFBGA, CSP, Flip Chip. The paper outlines lead-free ball analysis in comparison to conventional solder balls for BGA and chip size packages. The important points of interest are the description of processability related to existing ball attach procedures, requirements of interconnection properties and the knowledge gained the board level reliability. Both are the primary acceptance criteria for implementation. Knowledge about melting characteristic, surface tension depend on temperature and organic vehicles, wetting behavior, electrical conductivity, thermal conductivity, specific heat, mechanical strength, creep and relaxation properties, interactions to preferred finishes (minor impurities), intermetallic growth, content of IMC, brittleness depend on solved elements/IMC, fatigue resistance, damage mechanism, affinity against oxygen, reduction potential, decontamination efforts, endo-/exothermic reactions, diffusion properties related to finishes or bare materials, isothermal fatigue, thermo-cyclic fatigue, corrosion properties, lifetime prediction based on board level results, compatibility with rework/repair solders, rework temperatures of modified solders (Impurities, change in the melting point or range), compatibility to components and laminates.

• Journal of the Korean Vacuum Society
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• v.13 no.3
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• pp.127-131
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• 2004

Package reliability test was conducted to investigate the effect of solder composition on the ball fatigue strength for BGA (Ball Grid Array) packaging. The test pieces are assembled using eutectic composition 63Sn/37Pb, 62Sn/36Pb/2Ag, and 63Sn/34.4Pb/2Ag/0.5Sb solder after pre-conditioning at MRT Lv 3 (Moisture Resistance Test Level) and then conducted under T/C (Temperature Cycle test). For each case, the ball shear strength was obtained and micro structure photos were taken. SEM (scanning electron microscope) and EDX (Energy Dispersive X-ray) were used to the analyze failure mechanism. The growth rate of Au-Sn intermetallic compound in Sn63Pb34.5Ag2Sb0.5 solder was slow when compared to 63Sn/37Pb solder and 62Sn/36Pb/2Ag solder. The degradation of shear strength of solder balls caused by solder composition was discussed.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.289-299
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• 2005

The ball shear force was investigated in terms of test parameters, i.e. displacement rate and probe height, with an experimental and non-linear finite element analysis for evaluation of the solder joint integrity in area array packages. The increase in the displacement rate and the decrease in the probe height led to the increase in the shear force. Excessive probe height could cause some detrimental effects on the test results such as unexpected high standard deviation and probe sliding from the solder ball surface. The low shear height conditions were favorable for assessing the mechanical integrity of the solder joints. The mechanical and electrical properties of the Sn-37Pb/Cu and Sn-3.5Ag/Cu BGA solder joints were also investigated with the number of reflows. The total thickness of the intermetallic compound (IMC) layers, consisting of Cu6Sn5 and Cu3Sn, was increased as a function of cubic root of reflow time. The shear force was increased up to 3 or 4 reflows, and then was decreased with the number of reflows. The fracture occurred along the bulk solder, in irrespective of the number of reflows. The electrical resistivity was increased with increasing the number of reflows.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.4
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• pp.65-70
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• 2008

The mechanical shear strength of BGA(Ball Grid Array) solder joints under high impact loading was investigated. The Sn-37Pb solder balls with a diameter of $500{\mu}m$ were placed on the pads of FR-4 substrates with ENIG(Electroless Nickel Immersion Gold) surface treatment and reflowed. For the High Temperature Storage(HTS) test, the samples were aged a constant testing temperature of $120^{\circ}C$ for up to 250h. After the HTS test, high speed shear tests with various shear speed of 0.01, 0.1, 1, 3 m/s were conducted. $Ni_3Sn_4$ intermetallic compound(IMC) layer was observed at the solder/Ni-P interface and thickness of IMC was increased with aging process. The shear strength increased with increasing shear speed. The fracture surfaces of solder joints showed various fracture modes dependent on shear speed and aging time. Fracture mode was changed from ductile fracture to brittle fracture with increasing shear speed.

• Journal of Sensor Science and Technology
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• v.21 no.1
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• pp.34-38
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• 2012

We have developed a cost effective test socket for ball grid array(BGA) integrated circuit(IC) packages using BeCu metal sheet as a test probe. The BeCu furnishes the best combination of electrical conductivity and corrosion resistance. The probe of the test socket was designed with a BeCu cantilever. The cantilever was designed with a length of 450 ${\mu}m$, a width of 200 ${\mu}m$, a thickness of 10 ${\mu}m$, and a pitch of 650 ${\mu}m$ for $11{\times}11$ BGA. The fabrication of the test socket used techniques such as through-silicon-via filling, bonding silicon wafer and BeCu metal sheet with dry film resist(DFR). The test socket is applicable for BGA IC chip.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.11a
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• pp.27-32
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• 2002

In this paper, global full 3D finite element analysis fatigue models are constructed for flip-chip BGA on board to predict the creep fatigue life of solder joints during the thermal cycling test. The fatigue model applied is based on Darveaux's empirical equation approach with non-linear viscoplastic analysis of solder joints. It was estimated by the creep life as the variations of the four kinds of thermal cycling test conditions, pad structure, composition and size of solder ball. The shortest fatigue life of results was obtained at the thermal cycling testing condition of -65℃ ∼ 150℃. It was increased about 3.5 times in comparison with that of 0℃ ∼ 100℃. As the change of pad structure at the same other conditions, the fatigue life of SMD structure increased about 5.7% as compared with NSMD structure. Consequently, it was confirmed that the fatigue life became short as the creep strain energy density increased in solder joint.