• 마이크로전자및패키징학회지
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• 제19권3호
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• pp.37-41
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• 2012

Cu 본딩을 이용한 웨이퍼 레벨 적층 기술은 고밀도 DRAM 이나 고성능 Logic 소자 적층 또는 이종소자 적층의 핵심 기술로 매우 중요시 되고 있다. Cu 본딩 공정을 최적화하기 위해서는 Cu chemical mechanical polishing(CMP)공정 개발이 필수적이며, 본딩층 평탄화를 위한 중요한 핵심 기술이라 하겠다. 특히 Logic 소자 응용에서는 ultra low-k 유전체와 호환성이 좋은 Ti barrier를 선호하는데, Ti barrier는 전기화학적으로 Cu CMP 슬러리에 영향을 받는 경우가 많다. 본 연구에서는 웨이퍼 레벨 Cu 본딩 기술을 위한 Ti/Cu 배선 구조의 Cu CMP 공정 기술을 연구하였다. 다마싱(damascene) 공정으로 Cu CMP 웨이퍼 시편을 제작하였고, 두 종류의 슬러리를 비교 분석 하였다. Cu 연마율(removal rate)과 슬러리에 대한 $SiO_2$와 Ti barrier의 선택비(selectivity)를 측정하였으며, 라인 폭과 금속 패턴 밀도에 대한 Cu dishing과 oxide erosion을 평가하였다.

• ETRI Journal
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• 제39권2호
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• pp.284-291
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• 2017

Drain-induced barrier lowering (DIBL) is one of the main parameters employed to indicate the short-channel effect for nano metal-oxide semiconductor field-effect transistors (MOSFETs). We propose a new physical model of the DIBL effect under two-dimensional approximations based on the energy-conservation equation for channel electrons in FETs, which is different from the former field-penetration model. The DIBL is caused by lowering of the effective potential barrier height seen by the channel electrons because a lateral channel electric field results in an increase in the average kinetic energy of the channel electrons. The channel length, temperature, and doping concentration-dependent DIBL effects predicted by the proposed physical model agree well with the experimental data and simulation results reported in Nature and other journals.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2001년도 추계학술대회논문집 I
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• pp.133-138
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• 2001

Traffic noise is a significant national problem in many communities. Construction of noise barriers has been the most often used mechanism to mitigate vehicle noise for residents next to high density roadways. The most common materials for constructing noise barriers are metal. The character of the wall can be significantly modified by the type of surface treatment used on the wall body. Noise barrier walls can be softened through the use of plants. Greening Noise Barrier helps blend the roadway into the surrounding landscape and provides an interesting and aesthetic view of the road.

• ETRI Journal
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• 제13권4호
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• pp.88-93
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• 1991

본 연구에서는 게이트의 Schottky 접촉을 먼저 만들고 옴 접촉 공정을 그후에 하는 자기정렬 공정 (self-aligned process) 에서 다이오드의 특성 저하를 막기위하여, 내열성 금속 (refractory metal) 을 사용하여 두께와 온도에 따른 각각의 특성을 알아보았다. 내열성 금속으로는 텅스텐을 사용하였으며, 텅스텐이 게이트 금속인 Au 나 AlGaAs 에 대해 어느정도 확산에 대한 barrier의 역할을 하는 지에 대하여 알아보았다. 전류-전압 측정자료와 Auger 분석을 통하여 옴 접촉조건($480^{\circ}C$)에서 텅스텐의 두께가 30nm 이하에서는 barrier 의 역활이 어려운 것으로 나타났다. 그리고 30~60 nm 사이에서 트랜지스터의 특성에 있어서 많은 변화가 있음을 알 수가 있었으며, 90 nm 이상에서는 $530^{\circ}C$ 이상의 온도에서 Au에 대해 좋은 barrier 의 역활을 할 수 있는 것으로 나타났다.

• 한국전기전자재료학회논문지
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• 제16권2호
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• pp.97-101
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• 2003

New Pt/Ti and hi/Ti double-metal structures have been investigated for the application of a diffusion barrier between Cu and Si in deep submicron integrated circuits. Pt/Ti and Ni/Ti were deposited using E-beam evaporator at room temperature. The performance of Pt/Ti and Ni/Ti structures as diffusion barrier against Cu diffusion was examined by charge pumping method, gate leakage current, junction leakage current, and SIMS(secondary ion mass spectroscopy). These evaluation indicated that Pt/Ti(200${\AA}$/100${\AA}$) film is a good barrier against Cu diffusion up to 450$^{\circ}C$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.94-99
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• 2004

silicided 50-nm-gate-length n-type Schottky barrier metal-oxide-semiconductor field-effect-transistors (SB-MOSFETs) with 5 nm gate oxide thickness are manufactured. The saturation current is $120{\mu}A/{\mu}m$ and on/off-current ratio is higher than $10^5$ with low leakage current less than $10{\mu}A/{\mu}m$. Novel phenomena of this device are discussed. The increase of tunneling current with the increase of drain voltage is explained using drain induced Schottky barrier thickness thinning effect. The abnormal increase of drain current with the decrease of gate voltage is explained by hole carrier injection from drain into channel. The mechanism of threshold voltage increase in SB-MOSFETs is discussed. Based on the extracted model parameters, the performance of 10-nm-gate-length SB-MOSFETs is predicted. The results show that the subthreshold swing value can be lower than 60 mV/decade.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 광주전남지부
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• pp.87-90
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• 2006

Two SiC radiation detector samples were irradiated by Co-60 gamma rays. The irradiation was performed with dose rates of 5 kGy/hour and 15 kGy/hour for 8 hours, respectively. Metal/semiconductor contacts on the surface were fabricated by using a thermal evaporator in a high vacuum condition. The SiC detectors have metal contacts of Au(2000 ${\AA}$)/Ni(300 ${\AA}$) at Si-face and of Au(2000 ${\AA}$)/Ti(300 ${\AA}$) at C-face. I-V characteristics of the SiC semiconductor were measured by using the Keithley 4200-SCS parameter analyzer with voltage sources included. From the I-V curve, we analyzed the Schottky barrier heights(SBHs) on the basis of the thermionic emission theory. As a result, the 6H-SiC semiconductor showed- similar Schottky barrier heights independent to the dose rates of the irradiation with Co-60 gamma rays.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.251-252
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• 2012

Recently, the growing interest in organic microelectronic devices including OLEDs has led to an increasing amount of research into their many potential applications in the area of flexible electronic devices based on plastic substrates. However, these organic devices require a gas barrier coating to prevent the permeation of water and oxygen because organic materials are highly susceptible to water and oxygen. In particular, high efficiency OLEDs require an extremely low Water Vapor Transition Rate (WVTR) of $1{\times}10^{-6}g/m^2$/day. The Key factor in high quality inorganic gas barrier formation for achieving the very low WVTR required ($1{\times}10^{-6}g/m^2$/day) is the suppression of defect sites and gas diffusion pathways between grain boundaries. In this study, we developed an $Al_2O_3$ nano-crystal structure single gas barrier layer using a Neutral Beam Assisted Sputtering (NBAS) process. The NBAS system is based on the conventional RF magnetron sputtering and neutral beam source. The neutral beam source consists of an electron cyclotron Resonance (ECR) plasma source and metal reflector. The Ar+ ions in the ECR plasma are accelerated in the plasma sheath between the plasma and reflector, which are then neutralized by Auger neutralization. The neutral beam energies were possible to estimate indirectly through previous experiments and binary collision model. The accelerating potential is the sum of the plasma potential and reflector bias. In previous experiments, while adjusting the reflector bias, changes in the plasma density and the plasma potential were not observed. The neutral beam energy is controlled by the metal reflector bias. The NBAS process can continuously change crystalline structures from an amorphous phase to nano-crystal phase of various grain sizes within a single inorganic thin film. These NBAS process effects can lead to the formation of a nano-crystal structure barrier layer which effectively limits gas diffusion through the pathways between grain boundaries. Our results verify the nano-crystal structure of the NBAS processed $Al_2O_3$ single gas barrier layer through dielectric constant measurement, break down field measurement, and TEM analysis. Finally, the WVTR of $Al_2O_3$ nano-crystal structure single gas barrier layer was measured to be under $5{\times}10^{-6}g/m^2$/day therefore we can confirm that NBAS processed $Al_2O_3$ nano-crystal structure single gas barrier layer is suitable for OLED application.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.279-282
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• 2001

The IBE(ion beam etching)-induced Schottky barrier variation which depends on various etching history related with ion energy, incident angle and etching time has been investigated using voltage-current, capacitance-voltage characteristics of metal-etched silicon contact and morphology of etched surface were studied using AFM(atomic force microscope). For ion beam etched n-type silicons, Schottky barrier is reduced according to ion beam energy. It can be seen that amount of donor-like positive charge created in the damaged layer is proportional to the ion energy. By contrary, for ion beam etched p-type silicons, the Schottky barrier and specific contact resistance are both increased. Not only etching time but also incident angle of ion beam has an effect on barrier height. Taping-mode AFM analysis shows increased roughness RMS(Root-Mean-Square) and depth distribution due to ion bombardment. Annealing in an N$_2$ ambient for 30 min was found to be effective in improving the diode characteristics of the etched samples and minimum annealing temperatures to recover IBE-induced barrier variation were related to ion beam energy.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 춘계학술발표대회
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.