• Journal of the Korea Society for Simulation
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• v.10 no.1
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• pp.25-34
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• 2001

In this paper, we describe the generation method of interface logic which replace between IP & IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new asynchronous sequential "Waveform to VHDL" code creation algorithm by flow chart conversion : Wave2VHDL - if only mixed asynchronous timing waveform is presented the level type input and pulse type input for handshaking, we convert waveform to flowchart and then replace with VHDL code according to converted flowchart. Also, we confirmed that asynchronous electronic circuits are created by applying extracted VHDL source code from suggest algorithm to conventional domestic/abroad CAD Tool, Finally, we assured the simulation result and the suggest timing diagram are identical.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.771-774
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• 1999

This paper presents a new timing structure for real time communications and its performance analysis. The cycle time consists of several "one time slot" which may be an interval defined by a synchronous traffic part followed by an asynchronous traffic part. If a station receives a token within a synchronous interval, it transmits its synchronous message if any, otherwise it may transmit an asynchronous message. This scheme is different from usual allocation schemes which divide one cycle into alternating synchronous and asynchronous subslots. This protocol is designed to prevent low priority messages from delaying too much due to lots of high priority messages. We propose the algorithm and show its justification by simulation.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.7
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• pp.501-508
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• 2004

In this paper, a coordinated scheduling algorithm is proposed to reduce end-to-end delay in distributed control of systems. For the algorithm, the analysis of practical end-to-end delay in the worst case is performed priory with considering implementation of the systems. The end-to-end delay is composed of the delay caused by multi-task scheduling of operating systems, the delay caused by network communications, and the delay caused by asynchronous timing between operating systems and network communications. Through some simulation tests based on CAN(Controller Area Network), the proposed worst case end-to-end delay analysis is validated. Through the simulation tests, it is also shown that a real-time distributed control system designed to existing worst case delay cannot guarantee end-to-end time constraints. With the analysis, a coordinated scheduling algorithm is proposed here. The coordinated scheduling algorithm is focused on the reduction of the delay caused by asynchronous timing between operating systems and network communications. Online deadline assignment strategy is proposed for the scheduling. The performance enhancement of the distributed control systems by the scheduling algorithm is shown through simulation tests.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.34-42
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• 2005

In orthogonal frequency-division multiple access (OFDMA) uplink environments, asynchronously received signals can cause multiple access interference (MAI). This paper focuses on the performance degradation due to the MAI over frequency-selective fading channels. We first introduce the timing misalignment, which is defined as the relative timing difference between asynchronous timing error of uplink user and reference time of the base station, and analytically derive the MAI using the power delay profile of wide-sense stationary uncorrelated scattering (WSSUS) channel model. Then, the effective signal-to-noise ratio (SNR) and the average symbol error probability (SEP) are derived. The proposed analytical results are verified through simulations with respect to the region of the timing misalignment and the number of asynchronous users.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.05a
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• pp.82-87
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• 2001

In this paper we described the generation method of interface logic which can be replace between IP and IP handshaking signal with asynchronous logic circuit. Especially, we suggest the new \"Waveform Conversion Algorithm : Wave2VHDL\", if only mixed asynchronous timing waveform suggested which level type input and pulse type input for handshaking, we can convert waveform to flowchart and then replaced with VHDL code according to converted flowchart. Also, we assure that asynchronous electronic circuits for IP interface are generated by applying extracted VHDL source code from suggested algorithm to conventional domestic/abroad CAD Tool, and then we proved that coincidence simulation result and suggested timing diagram.g diagram.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.61-74
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• 2002

This paper presents a method which synthesizes asynchronous circuits from free-choice Signal Transition Graphs (STGs) with timing constraints. The proposed method synthesizes asynchronous circuits by analyzing: the relations between signal transitions directly from the STGs without generating state graphs. The synthesis procedure decomposes a free-choice STG into deterministic STGs which do not have choice behavior. Then, a timing analysis extracts the timed concurrency and tamed causality relations between any two signal transitions for each deterministic STG. The synthesis procedure synthesizes circuits for each deterministic STG and synthesizes the final circuit by merging the circuits for each deterministic STG. The experimental results show that our method achieves significant reductions in synthesis time for the circuits which have a large state space, and generates circuits that have nearly the same area as compared to previous methods.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.216-226
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• 2000

This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a deterministic signal transition graph specification with timing constraints. First, a timing analysis extracts the timed concurrency and timed causality relations between any two signal transitions. Then, a hazard-free implementation under the timing constraints is synthesized by constructing a precedence graph and finding paths in the graph. The major result of this work is that the method does not suffer from the state explosion problem, achieves significant reductions in synthesis time, and generates circuits that have nearly the same area as compared to previous methods.

• ETRI Journal
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• v.35 no.3
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• pp.480-490
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• 2013

As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large-scale asynchronous circuit, we design a fully clockless 32-bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top-down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre-layout simulation utilizing 0.13-${\mu}m$ CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 ${\mu}W$/MHz and is comparable to that of a synchronous counterpart.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.4
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• pp.161-171
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• 2015

Alternative binary offset carrier (AltBOC) signals can be approximated by four synchronized direct sequence spread spectrum (DSSS) signals, each pair of which is a quadrature phase shift keyed (QPSK) signal at a different frequency. Therefore, depending on the strength of an incoming AltBOC signal, an acquisition technique can reduce the mean acquisition time (MAT) by searching the four DSSS signals asynchronously; the search for each of the four DSSS signals can start at one of the evenly separated hypotheses on the two-dimensional hypothesis space. And detection sensitivity can be improved by multiple levels when different numbers of search results for the same hypothesis are combined. In this paper, we propose a fast AltBOC acquisition technique that has an asynchronous search strategy and efficiently utilizes the output of the four search results to increase the sensitivity level when sensitivity improvement is needed. We provide a complete theoretical analysis and demonstrate with numerous Monte Carlo simulations that the MAT of the proposed technique is much smaller than conventional AltBOC acquisition techniques.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.1-8
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• 2010

This paper models a symbol timing offset (STO) with respect to the guard period and the maximum access delay time for asynchronous multicarrier code division multiple access (MC-CDMA) uplink systems over frequency-selective multipath fading channels. Analytical derivation shows that STO causes desired signal power degradation and generates self-interferences. This effect of the STO on the average bit error rate (BER) and the effective signal-to-noise ratio (SNR) is evaluated. The approximated BER and the SNR loss caused by STO are then obtained as closed-form expressions. The tightness between the analytical result and the simulated one is verified for the different STOs and SNRs. Furthermore, the derived analytical results are verified via Monte Carlo simulations.