• Proceedings of the Korean Society of Marine Engineers Conference
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• 2011.10a
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• pp.73-73
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• 2011

In fact, asynchronous motors are used widely. Asynchronous motors which have large power (compared to the source supplies) is needed to start them in various methods. The theory of application reduced voltage to motor's stator or variable resistor fed rotor for the purpose of altering the motor's torque and power consumption characteristics is an idea that has existed for many years. These concepts have flourished mainly due to the need to limit torque and limited generator/power distribution capabilities. However, how can know exactly the time of switching steps with different types of motors as well as load characteristics is very difficult. This paper focuses on the design and development mathematical models of motor[1][2], load, ACB, asynchronous machine and then is implemented in SIMULINK in order to calculate this time, special on ships where power generation station is limited. The simulation results are both compared and discussed in detail so that it can apply to conclude the most suitable and applicable starting time for new system with various motors and load.

• The Journal of the Korea Contents Association
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• v.12 no.7
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• pp.11-20
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• 2012

This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.67-74
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• 2004

Most of today's parallel numerical schemes use synchronous algorithms, where some processors that have finished their tasks earlier than others must wait at synchronization points for correct computation. Hence overall performance of the system is dependent upon the speed of the slowest processor. In this paper, we det·ise a synchronous/asynchronous hybrid algorithm to accelerate convergence of the solution for finding the dominant eigenpair of a large matrix, by reducing the idle times of faster processors using MPMD programming methodology.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.353-356
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• 2002

Due to the increased complexity and size of digital system and the need of the H/W-S/W co-design, C/C++ based system design methodology gains more Interests than ever in EDA field. This paper suggests the methodology in which handshake module corresponding to each basic statement of C is provided of the form of STG(Signal Transition Graph) and then, C statements is synthesized into asynchronous circuit through syntax-oriented translation. The 4-phase handshaking protocol is used for the communications between modules, and the modules are synthesized by the Petrify which is asynchronous logic synthesis CAD tool.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.36-44
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• 2007

This paper presented a hybrid ternary encoding scheme using 3-valued logic. It can adapt to the delay-insensitive(DI) model. We designed an asynchronous wrapper for the hybrid ternary encoding scheme to communicate with various asynchronous encoding schemes. It reduced about 50% of transmission lines and power consumption compared with the conventional 1-of-4 and ternary encoding scheme. The proposed wrappers were designed and simulated using the $0.18-{\mu}m$ standard CMOS technology. As a result, the asynchronous wrapper operated over 2 GHz communicating with a system bus. Moreover, the power dissipation of the system bus adapted the hybrid ternary encoding logic decreases 65%, 43%, and 36% of the dual-rail, 1-of-4, and ternary encoding scheme, respectively. The proposed data encoding scheme and the wrapper circuit can be useful for asynchronous high-speed and low-power asynchronous interface.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.2661-2663
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• 2005

To construct the stable back-up system between mini-hubs, we propose the plan of site diversity of asynchronous mini-hub by monitoring outlink carriers and error data. In this paper, we made hardware and software to control mini-hub system for site diversity back-up by switching SDBS equipment through communication between master mini-hub and slave mini-hub.

• Journal of the Korean Society of Safety
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• v.12 no.3
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• pp.67-75
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• 1997

This paper presents a study on the application of Asynchronous Team(A-Team) theory for QVC(Reactive power control) and security assessment in a power system. Reactive power control problem is the one of optimally establishing voltage level given reactive power sources, which is very important problem to supply the demand without interruption and needs methods to alleviate a bus voltage limit violation more quickly. It can be formulated as a mixed-integer linear programming(MILP) problem without deteriorating of solution accuracy to a certain extent. The security assessment is to estimate the relative robustness of the system and deterministic approach based on AC load flow calculations is adopted to assess it, especially voltage security. A distance measure, as a measurement for voltage security, is introduced. In order to analyze the above two problem, reactive power control and static security assessment, In an integrated fashion, a new organizational structure, called an A-team, is adopted. An A-team is well-suited to the development of computer-based, multi-agent systems for operation of large-scaled power systems. In order to verify the usefulness of the suggested scheme herein, modified IEEE 30 bus system is employed as a sample system. The results of a case study are also presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2021-2026
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• 2007

In the parer, we design a non-coherent UWB system by adopting the architecture of a simplified asynchronous transmission and the edge-triggered pulse transmission, which makes e system performance independent of the share of the transmitted waveform, robust to multipath channels. The designed non-coherent UWB transceiver architecture has an advantage of the simple realization since any mixer, high-speed correlator, and high-sampling A/D converter are not necessary at the cost of performance degradation of about 3dB. Further, the designed non-coherent UWB transceiver is actually implemented with the wireless CANVAS prototype testbed in short range indoor application environments such as a lecture room. The implemented prototype testbed is proven to offer the data rate of 115kbps on the conditions of Peer-to-Peer(P-to-P) in the indoor channel within the range of about 10m.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.4
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• pp.7-14
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• 2010

Stable-state behaviors of asynchronous sequential machines represented as finite state machines can be corrected by feedback control schemes. In this paper, we propose a state feedback control scheme for input/state asynchronous machines with uncertain transitions. The considered asynchronous machine is deterministic, but its state transition function is partially known due to model uncertainty or inner logic errors. The control objective is to compensate the behavior of the closed-loop system so that it matches a sub-behavior of a prescribed model despite uncertain transitions. Furthermore, during the execution of corrective action, the controller reflects the exact knowledge of transitions into the next step, i.e., the range of the behavior of the closed-loop system can be enlarged through learning. The design procedure for the proposed controller is described in a case study.