Browse > Article
http://dx.doi.org/10.5392/JKCA.2010.10.6.072

Design of an Asynchronous Data Cache with FIFO Buffer for Write Back Mode  

Park, Jong-Min (충북대학교 정보통신 공학과)
Kim, Seok-Man (충북대학교 정보통신 공학과)
Oh, Myeong-Hoon (한국전자통신연구원 서버플랫폼 연구팀)
Cho, Kyoung-Rok (충북대학교 전자정보대학)
Publication Information
The Journal of the Korea Contents Association / v.10, no.6, 2010 , pp. 72-79 More about this Journal
Abstract
In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.
Keywords
Data Cache; Write Buffer; Asynchronous FIFO; Asynchronous System;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 전광배, 김석만, 이제훈, 오명훈, 조경록, “혼합 지연 모델에 기반한 비동기 명령어 캐시 설계”, 한국콘텐츠학회논문지, 제10권, 제3호, pp.64-71, 2010(3).   과학기술학회마을   DOI
2 Virantha N. Ekanayak and Rajit Manohar, "Asynchronous DRAM Design and Synthesis," Proc. Asynchronous Circuits and Systems, pp.174-183, 2003(5).
3 J. Pangjun and S. Sapatnekar, "Low-power Clock Distribution Using Multiple Voltages and Reduced Swings," IEEE Journal of TVLSI, Vol.10, No.2, pp.309-319, 2002(6).
4 X. Wang, T. Ahonen, and J. Nurmi, "A Synthesizable RTL Design of Asynchronous FIFO," Proc. ISSOC'2004, pp.123-128, 2004(11).
5 Z. Wang, S. Das, h. Che, and M. Kumar, "SACCS: Scalable Asynchronous Cache Consistency Scheme for Mobile Environments," Proc. ICDCSW'2003, pp.797-802, 2003(5).
6 S. N. Kim, S. W. Kim, Y. W. Kim. M. H. Oh, and C. H. Shin, "Ultra low power asynchronous processor development," Technical Report 09ZH1230-01-7030p, ETRI, 2009(12).
7 D. Hormdee and J. D. Ringenberg, D Ernst, T. M. Austin, T. R. Mudge, and B. Brown, "MiBench: A free, commercially representative embedded benchmark suite," Proc. WWC-4.2001, pp.3-14, 2001(12).
8 D. Hormdee and J. D. Garside, "AMULET3i cache architecture," Proc. ASYNC'2001, pp.152-161, 2001(5).