• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.759-762
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• 1998

In this paper, a SL-DCVSL (static latched differential cascode voltage switch logic) circuit for the asynchronous pipeline is proposed. The proposed SL-DCVSL circuit is a slightly modified version of the DCVSL circuit, and used to improve the storage capability of the precharged functional blocks. The proposed SL-DCVSL has more robust storage characteristics compared to the conventional LDCVSL (latched DCVSL〔2〕). The operation of the proposed circuit is verified by simulating the asynchronous FIFO (First-In First-Out) structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.931-933
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• 2004

In a SoC environment, asynchronous design techniques offer solutions for problems of synchronous design techniques. Asynchronous FIFOs have the advantages of easier interconnection methods and higher throughput than synchronous ones. Low latency and high throughput are two imp ortant standards in asynchronous FIFOs. We present low latency asynchronous FIFO in the paper, which optimizes GasP[6]. Pre-layout of HSPICE simulations of a 8-stage FIFO on 1-bit datapath using Anam's 0.25$\mu\textrm{m}$ technology indicates 17% lower latency than GasP.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.109-112
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• 2002

This paper presents relationship between the dynamic behavior of an asynchronous linear pipeline (ALP) and the performance of the ALP as buffers are allocated. Then the relationship is used in order to characterize a local optimum situation on the buffer design space of the ALP. Using the characterization we propose an efficient algorithm optimizing buffer allocation on an ALP in order to achieve its average case performance. Without the loss of optimality, our algorithm works in linear time complexity so it achieves fast buffer-configuration optimization. This paper makes two contributions. First, it describes relationship between the performance characteristics of an ALP and a local optimum on the buffer design space of the ALP. Second, it devises a buffer allocation algorithm finding an optimum solution in linear time complexity.

• Journal of Korea Society of Industrial Information Systems
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• v.22 no.1
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• pp.53-59
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• 2017

This Paper Proposes a New High-speed Design Methodology for Delay Insensitive Asynchronous Circuits Combining with a Pseudo-NMOS Structure used for High Performance in Synchronous Circuits. Null Convention Logic(NCL) of Conventional Delay-Insensitive Asynchronous Design Methodologies has many Advantages of High Reliability, Low Power Consumption, and Easy Design Reuses not Dependant on Semiconductor Technology. However. the Conventional NCL Gates has a Complicated Stack Structure, so it Suffers from Increased Circuit Delay. Therefore, a New NCL Gates and its Pipeline Structure for High Performance, and the Proposed Methodology has been Designed and Evaluated by a $4{\times}4$ Multiplier Designed using SK-Hynix 0.18 um CMOS Technology. The Experimental Results are Compared with a Conventional NCL in Terms of Power and Delay and shows that the Propagation Delay of the Proposed Multiplier is Reduced by 85% Compared with the Conventional NCL Multiplier.

• The Journal of the Korea Contents Association
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• v.12 no.7
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• pp.11-20
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• 2012

This paper presents new instruction-level power model for an asynchronous processor, A8051. Even though the proposed model estimates power consumption as instruction level, this model reflects the behavioral features of asynchronous pipeline during the program is executed. Thus, it can effectively enhance the accuracy of power model for an asynchronous embedded processor without significant complexity of power model as well as the increase of simulation time. The proposed power model is based on the implementation of A8051 to reflect the characteristics of power consumption in A8051. The simulation results of the proposed model is compared with that of gate-level synthesized A8051. The proposed power model shows the accuracy of 94% and the simulation time for estimation the power consumption was reduced to 1,600 times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.3
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• pp.33-42
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• 2003

This paper describes an efficient design of an asynchronous 16-bit divider using the NST (new Svoboda-Tung) algorithm. The divider is designed to reduce power consumption by using the asynchronous design scheme in which the division operation is performed only when it is requested. The divider consists of three blocks, i.e. pre-scale block, iteration step block, and on-the-fly converter block using asynchronous pipeline structure. The pre-scale block is designed using a new subtracter to have small area and high performance. The iteration step block consists of an asynchronous ring structure with 4 division steps for area reduction. In other to reduce hardware overhead, the part related to critical path is designed by a dual-rail circuit, and the other part is done by a single-rail circuit in the ring structure. The on-the-fly converter block is designed for high performance using the on-the-fly algorithm that enables parallel operation with iteration step block. The design results with 0.6${\mu}{\textrm}{m}$ CMOS process show that the divider consists of 12,956 transistors with 1,480 $\times$1,200${\mu}{\textrm}{m}$$^2$area and average-case delay is 41.7㎱.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.5
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• pp.511-520
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• 1989

Generally, Intelliget link is made of drawing picture that is amalgated in two conception of communication and processing. This is a new system of information transmission having fuction being able to handle een though the former information transmission can not be possible. That Intelligent link is to say that function of each segment by working software can be anailable at general purposed pipeline processing system, general purpose pipeline have a different working time in function of segmant, work asynchronizing pipeline. in the papers, graphic design is easy to understand the sense of sight model by Petri Net that is simple regulation. it can translate into working of asynchronzing pipeline by working of calculator of simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1380-1385
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• 2006

A Pipelined Tone Wakeup(PTW) scheme(1) was proposed to support energy saving and end-to-end delay for sensor networks by providing an asynchronous wakeup pipeline to overlap the wakeup procedures with the packet transmission. But the scheme uses two radios and assumes error-free environments. In this paper, we propose a modified PTW scheme for wireless sensor networks. The proposed scheme is based on the PTW. The difference is that next hop information will be included in the ack packet from receiver node to sender node, So all the other neighbor nodes can stay in sleep mode long enough to save energy. Also ore get enhanced delay performance.