• Journal of Korea Multimedia Society
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• v.19 no.3
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• pp.567-572
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• 2016

N-screen is an emerging technology to support multimedia multicasting, content sharing and content mobility. N-screen service providers should obtain the technology that provides the highest quality content seamlessly. Distributed nature of WiMedia distributed-MAC protocol can provide full mobility support, and achieves seamless medium access method in contrast to IEEE 802.15.3. So, in this paper, WiMedia distributed-MAC protocol is adopted and an asynchronous multicast transmission (AMT) technology is proposed to enhance performance of seamless N-screen wireless service based on distributed-MAC. The ACK frame transmissions are not required for multicast transmissions. By using this property in AMT, if a device is a multicast receiver, its reserved time slots can be reserved by the other devices with 1-hop distance. Furthermore, each N-screen device broadcasts and shares the information including an order in asynchronous traffic reservations to reduce conflicts in determining the transmission order of asynchronous N-screen packets. Therefore, AMT scheme expands the number of time slots available and throughputs for multicast and asynchronous traffic reservations when comparing with the distributed-MAC standard system. N-screen communications based on distributed-MAC with the proposed AMT shows a new framework for realizing N-screen wireless service with the full content mobility.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.253-261
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• 2013

In this paper, we study the problem of controlling composite asynchronous sequential machines. The considered asynchronous machine consists of two input/state machines in cascade connection, where the output of the front machine is delivered to the input channel of the rear machine. The objective is to design a corrective controller realizing model matching such that the stable state behavior of the closed-loop system matches that of a reference model. Since the controller receives the state feedback of the rear machine only, there exists uncertainty about the present state of the front machine. We specify the existence condition for a corrective controller given the uncertainty. The design procedure for the proposed controller is described in a case study.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.635-640
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• 2002

We investigate optimal and suboptimal decision rules for parallel code acquisition in chip asynchronous direct-sequence spread-spectrum systems. The conventional decision rule for parallel acquisition is to choose the largest correlator output of a receiver. However, such a scheme is optimum only for chip synchronous models. In this paper, an optimal decision rule is derived based on the maximum-likehood criterion for chip asynchronous models. A simpler suboptimal decision rule is also discussed. The performance of the optimum and suboptimum decision rules is compared to that of the conventional decision rule. Numerical results show that, for chip asynchronous models, both the optimal and suboptimal decision rules outperform the conventional decision rule.

• The Journal of Engineering Research
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• v.1 no.1
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• pp.41-48
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• 1997

In this paper, we wxtend DMSA system to support multimedia traffic more efficiently by incorporating a priority scheme. we divide network stations into two types: asynchronous and isosynchronous stations, and we give a priority to the isosynchronous stations over the asynchronous stations by imposing a time-out constraint on the asynchronous stations . we derive the maximum number of isosynchronous stations the proposed priority scheme can support simultaneously and the maximum bandwidth that can be utilized by asynchronous stations in the presence of isosynchronous traffic. We also provide simulation results for the mixed voice and data traffic, and compare them to the analytic results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.11
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• pp.1271-1278
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• 1992

In this paper, a practical model for evaluating and comparing the bit error rates(BERs) due to adjacent channel mutual interference in a synchronous and asynchronous frequency hopped spread spectrum multiple access(FH-SSMA) radio communication systems is proposed. After implementing the actual FH radio in both the sychronous and asynchronous case, the BER is computed and measured. An experiment of this system in mobile tactical environments reveals that the performance in the asynchronous case is lower than that of the synchronous case. The computer simulation model is an efficient tool for designing practical FH radios in mobile communication environments.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.43-48
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• 2023

This paper discusses the design of 32Mbyte asynchronous nonvolatile memory modules, which includes self-diagnosis and RTC (Real Time Clock) functions to enhance their data stability and reliability. Nonvolatile memory modules can maintain data even in a power-off state, thereby improving the stability and reliability of a system or device. However, due to the possibility of data error due to electrical or physical reasons, additional data loss prevention methods are required. To minimize data error in asynchronous nonvolatile memory modules, this paper proposes the use of voltage monitoring circuits, self-diagnosis, BBT (Bad Block Table), ECC (Error Correction Code), CRC (Cyclic Redundancy Check)32, and data check sum, data recording method using RTC. Prototypes have been produced to confirm correct operation and suggest the possibility of commercialization.

• Journal of Power Electronics
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• v.9 no.2
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• pp.267-274
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• 2009

This paper deals with a voltage and frequency (VF) controller for an isolated power generation system based on an asynchronous generator (AG) driven by a pico hydro turbine. The proposed controller is a combination of a static compensator (STATCOM) and an electronic load controller (ELC) for decoupled control of the reactive and active powers of the AG system to control the voltage and frequency respectively. The proposed generating system along with its VF controller is modeled in MATLAB using SIMULINK and PSB (Power System Block Sets) toolboxes. The performance of the controller is verified for the proposed system and feeding various types of consumer load such as linear/non-linear, balanced/unbalanced and dynamic loads.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.349-352
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• 2001

As microprocessor and SOC (System On a Chip) performance moves into the GHz speed, the high-speed asynchronous design is becoming challenge due to the disadvantageous power and speed aspects in synchronous designs. The next generation on-chip systems will consist of multiple independently synchronous modules and asynchronous modules for higher performance, so the interface module for data transfer between multiple clocked IPs is designed with Xilinx FPGA and simulated with RISC microprocessor.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.812-822
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• 1997

In this paper, we propose an architecture of the asynchronous shared-bus type switch with priority and fairness schemes. The switch architecture is an input and output queueing system, and the priority scheme is implemented in both input and output queues. We analyze packet delay of both input and output queues. In the analysis, we consider to stations with asymmetric arrival rates. Although we make some approximations in the analysis, the numerical results show good agreements with the simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1237-1243
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• 2004

This paper presents and analyses the closed-form expression of the average bit error rate (BER) for an asynchronous direct-sequence code division multiple access (DS-CDMA) system with coherent binary phase shift keying (BPSK) modulation scheme using a maximal ratio combining (MRC) diversity over a Rician fading channel. In addition to the average BER, outage probability, and user capacity of system are estimated as performance measures. The results are general enough so that it includes Rayleigh fading and nonfading channel with zero and infinite Rician factor, respectively, as special cases. The effects of various channel models, processing gains, and diversity orders on the system performances are also considered for the typical multipath delay profiles characterized by Rician fading channel.