• Journal of KIISE:Databases
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• v.29 no.6
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• pp.492-501
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• 2002

An asynchronous trigger processor (ATP) is a oftware system that processes triggers after update transactions to databases are complete. In an ATP, discrimination networks are used to check the trigger conditions efficiently. Discrimination networks store their internal states in memory nodes. TriggerMan is an ATP and uses Gator network as the .discrimination network. The changes in databases are delivered to TriggerMan in the form of tokens. Processing tokens against a Gator network updates the memory nodes of the network and checks the condition of a trigger for which the network is built. Parallel token processing is one of the methods that can improve the system performance. However, uncontrolled parallel processing breaks trigger processing semantic consistency. In this paper, we propose four trigger processing consistency levels that allow parallel token processing with minimal anomalies. For each consistency level, a parallel token processing technique is developed. The techniques are proven to be valid and are also applicable to materialized view maintenance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.10-19
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• 1986

This is the last part of the four-part describing the development of a packet-switched computer communication network named the KORNET. In this paper we describe the design and implementation of the packet assembler/dissassembler (PAD) protocol for the asynchronous channel service, and of the network management softwares. The line processing module-B(LPMB) system supporting the asynchronous line includes a PAD protocol, a packet mode DTE/DCE protocol converting to the X.25 protocol, and the asynchronous receiver/transmitter(ART) software. The network management software is operated in master central processing module(MCPM) which includes virtual circuit management (VCM) managing the user channel, the routing management and the high level protocol for communication between the network management center (NMC) and the network node processor(NNP). In this paper, the design, implementation and operation of the softwares for the above service functions will be described in detail.

• Journal of the Korea Convergence Society
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• v.7 no.1
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• pp.9-15
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• 2016

In this paper, we describe the design of a high speed data acquisition system(DAS) with STM32 processor based on Cortex-M4. The system is used for the sensor devices to collect raw data on production lines at factory and send them to the servo computer in real time. The system is designed for multi functions with universal asynchronous receiver and transmitter(UART), analog to digital converter(ADC), digital to analog converter(DAC), and general purpose input output(GPIO). those are well tested for various data acquisition and high speed motor control in real time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.1
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• pp.42-56
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• 2002

It is possible but not efficient to model and simulate asynchronous microprocessors with the existing HDLs(HARDware Description Languages) such as VHDL or Verilog. The reason it that the description becomes too complex. and also the simulation time becomes too long to explore the design space. Therefore it is necessary to establish a methodology and develop a tool for modeling the handshake protocol of asynchronous microprocessors very easily and simulating it very fast. Under this objective an efficient CAD(Computer Aided Design) tool SLEDS(System Level Event-Driven Simulator) was developed which can evaluate performance of a processor through modeling with a simple description an simulating with event driven engine in the system level. The ultimate goal in the tool SLEDS is to fin the optimal conditions for a system to produce high performance by balancing the delay of each module in the system. Besides SLEDS aims at verifying the design through comparing the expected results with the actual ones by performing the defined behavior.

• Journal of Power Electronics
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• v.14 no.6
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• pp.1139-1146
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• 2014

Digital signal processor (DSP) and field programmable gate array (FPGA) based concentrated control systems are designed for implementing CPS-SPWM strategies. The self-defined universal asynchronous receiver/transmitter (UART) protocol is used for communication between a master controller and an individual module controller via high speed links. Aimed at undesired pulse competition, this paper analyzes its generation mechanism and presents a new method for eliminating competition pulses with no time delay. Finally, the proposed concentrated controller is applied to a 10kV/10MVar distribution static synchronous compensator (DSTATCOM) industrial prototype. Experimental results show the accuracy and reliability of the concentrated controller, and verify the superiority of the proposed elimination method for competition pulses.

• The Transactions of the Korea Information Processing Society
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• v.6 no.1
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• pp.42-48
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• 1999

Consider the situation that informations necessary to solve a certain problem are distributed among processors on a network. It is called a distributed algorithm that in this situation each processor exchanges the message with adjacent processors to solve the problems. This paper proposes a distributed algorithm to solve the problem that constructs the weighted shortest path tree in an asynchronous network system. In general, a distributed algorithm is estimated by the number of messages(message complexity of the distributed algorithm proposed in this paper are O(n53) and O(nln) respectively. where n is the number of processors on the network.

• International Journal of Advanced Culture Technology
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• v.4 no.4
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• pp.30-37
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• 2016

In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.412-415
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• 1999

In this paper, we describe an implementation of the B-Link bus interface logic for a directory controller and a remote access cash controller in the SCI-based CC-NUMA multimedia server developed by ETRI . The CC-NUMA multimedia server is composed of a number of Pentium III SHV nodes and a SCI interconnection network. To communicate with remote nodes, each node has a CC-Agent which consists of a processor bus interface(PIF). a directory controller(DC), a remote access cash controller(RC), and two SCI 1ink controllers(LCs). The B-Link bus interface logic is developed for a directory controller and a remote access cash controller in order to communicate with a SCI link controller on a B-Link bus. It consists of a sending master controller a receiving slave controller, and asynchronous data buffers. And It performs a self-arbitration, a data packet transmission, a queue allocation, an early terminal ion. and a cut-through data path.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.249-251
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• 1994

This paper introduces an implementation of high performance voltage source inverter system based on 16bit micro-processor and DSP for the application to modem rolling stock traction system. In contrast with other industry oriented inverter system, this system requires precise control action complying with various load condition and high overload capability. An asynchronous PWM generation and 3' pulse mode technology are adopted in order to improve compliant starting torque characteristics at starting phase and soft backward-forward starting motion.