• Title/Summary/Keyword: Asynchronous Communication

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A Study on Frequency Modulation Method to Reduce Time Interval Error (주파수 변조 기법에 의한 시간격 오차 개선에 대한 연구)

  • Ahn, Tae-Won;Lee, Won-Seok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.2
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    • pp.141-146
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    • 2016
  • This paper presents a method to improve time interval error for asynchronous communication systems. The proposed method is designed and simulated with multi-phase VCO, interpolator, phase selector, up-down counter, comparator and adder. The simulation results for CAN communication system show that the maximum time interval error can be tightly managed for satisfying the required specification. The proposed frequency modulation method can be properly used for asynchronous communication systems requiring high reliability.

A Kernel-Level Communication Module for Linux Clusters (리눅스 클러스터를 위한 커널 수준 통신 모듈)

  • 박동식;박성용;양지훈
    • Journal of KIISE:Computing Practices and Letters
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    • v.9 no.3
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    • pp.289-300
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    • 2003
  • Traditional kernel-level communication systems for clusters are dependent upon computing platforms. Futhermore, they are not easy to use and do not provide various functions for clusters. This paper presents an architecture and various implementation issues of a kernel-level communication system, KCCM(Kernel level Cluster Communication Module), for linux cluster. The KCCM provides asynchronous communication services as well as standard synchronous communication services using send and receive. The KCCM also automatically detects and recovers connection failures at runtime. This allows programmers to use KCCM when they build mission critical applications over TCP-based connection-oriented communication environments. Having developed using standard socket interfaces, it can be easily ported to various platforms. The experimental results show that the KCCM provides good performance for asynchronous communication patterns.

Design of Asynchronous Library and Implementation of Interface for Heterogeneous System (비동기 라이브러리 설계와 Heterogeneous시스템을 위한 인테페이스 설계)

  • Jung, Hwi-Sung;Lee, Joon-Il;Lee, Moon-Key
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.9
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    • pp.47-54
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    • 2000
  • We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

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Fault-Tolerant Control of Input/Output Asynchronous Sequential Circuits with Transient Faults Violating Fundamental Mode (기본 모드를 침해하는 과도 고장이 존재하는 입력/출력 비동기 순차 회로에 대한 내고장성 제어)

  • Yang, Jung-Min;Kwak, Seong-Woo
    • The Journal of the Korea institute of electronic communication sciences
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    • v.17 no.3
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    • pp.399-408
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    • 2022
  • This paper proposes a corrective control system to achieve fault-tolerant control for input/output asynchronous sequential circuits vulnerable to transient faults violating fundamental mode operations. To overcome non-fundamental mode faults occurring in transient transitions of asynchronous sequential circuits, it is necessary to determine the end of unauthorized state transitions caused by the faults and to stably take the circuit from the faulty state to a desired state that is output equivalent with the normal next stable state. We address the existence condition for a proper output-feedback corrective controller that achieves fault diagnosis and fault-tolerant control for these non-fundamental mode faults. The corrective controller and asynchronous sequential circuit are implemented on field-programming gate array to demonstrate the synthesis procedure and applicability of the proposed control scheme.

The Implementation of the Solar Inverter Monitoring System using an AJAX (AJAX를 이용한 태양광 인버터의 모니터링 시스템 구현)

  • Kwon, Hyo-Sang;Yang, Oh
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.9
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    • pp.1915-1922
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    • 2012
  • In this paper, the Solar Inverter will be monitored by using the AJAX(Asynchronous JavaScript and XML). AJAX is the one of the technologies that can make the RIA(Rich Internet Application) with DHTML(Dynamic Hyper Text Makeup Language) and other java script technology. By using this, a strong application program that is comparable to the general application program can be made. With an existing data-processing technique, the request and response of data can't be processed dynamically on the same page. However, real-time monitoring of data and operation statuses can be confirmed by using the AJAX an asynchronous method of communication. Also without changing the page, the amount of data transmission used the AJAX with significantly small amounts of data to build a Solar Inverter monitoring system that is able to efficiently handle management and monitoring, operating all functions within one page.

Power Consumption Analysis of Asynchronous RIT mode MAC in Wi-SUN (Wi-SUN에서 비동기 RIT 모드 MAC의 전력소모 분석)

  • Dongwon Kim
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.23 no.4
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    • pp.23-28
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    • 2023
  • In a wireless smart utility network communication system, an asynchronous low power MAC is standardized and used according to IEEE 802.15.4e. An asynchronous MAC called RIT (Receiver Initiated Transmission) has a characteristic in which delay time and power consumption are greatly affected by a check-in interval (RIT period). By waking up from sleep every check-in interval and checking whether there is data to be received, power consumption in the receiving end can be drastically reduced, but power consumption in the transmitting end occurs due to an excessive wakeup sequence. If an excessive wake-up sequence is reduced by shortening the check interval, power consumption of the receiving end increases due to too frequent wake-up. In the RIT asynchronous MAC technique, power consumption performance according to traffic load and operation of check-in interval is analyzed and applied to Wi-SUN construction.

Project Work and Asynchronous Voice Communication (프로젝트 작업과 비실시간 음성 커뮤니케이션)

  • Kim Min-Kyung;Kim Hee-Cheol
    • Journal of Korea Multimedia Society
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    • v.9 no.5
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    • pp.681-690
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    • 2006
  • With the rapid development of network and multimedia technologies, computer mediated communication has been realized and there has been a great potential to use and research on asynchronous voice communication systems. This paper reports a case study where 6 groups(3 for documentation work, 3 for software development) of 24 people who used voice mail when carrying out their projects. The purpose of this study is to obtain an overall understanding of usability of voice mail which is a typical example of asynchronous voice communication systems, under a particular situation where project works are performed. Through the study, we came to understand general purposes of usage of voice mail, patterns of using it revealed during the project process, different ways of using it according to different types of projects, and reasons why people are currently not likely to use voice mail. The results hopefully provide systems developers with a guideline to understand the nature of voice mail from users' perspectives.

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Instruction-level Power Model for Asynchronous Processor (명령어 레벨의 비동기식 프로세서 소비 전력 모델)

  • Lee, Je-Hoon
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.7
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    • pp.3152-3159
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    • 2012
  • This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.

Site Diversity for Asynchronous Mini Hub (비동기 분산제어국 사이트 다이버시티 구현)

  • Shin, Gang-Wook;Hong, Sung-Taek;Lee, Dong-Keun;Choi, Kwang-Mook
    • Proceedings of the KIEE Conference
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    • 2005.07d
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    • pp.2661-2663
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    • 2005
  • To construct the stable back-up system between mini-hubs, we propose the plan of site diversity of asynchronous mini-hub by monitoring outlink carriers and error data. In this paper, we made hardware and software to control mini-hub system for site diversity back-up by switching SDBS equipment through communication between master mini-hub and slave mini-hub.

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Asynchronous Multiplier with Parallel Array Structure (병렬배열구조를 사용한 비동기 곱셈기)

  • Park, Chan-Ho;Choe, Byeong-Su;Lee, Dong-Ik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.87-94
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    • 2002
  • In this paper an asynchronous away multiplier with a parallel array structure is introduced. This parallel array structure is used to make the computation time faster with a lower Power consumption. Asymmetric parallel away structure is used to minimize the average computation time in an asynchronous multiplier. Simulation shows that this structure reduces the time needed for computation by 55% as compared to conventional booth encoding array structures and that the multiplier with the proposed away structure shows a reduction of 40% in the computational time with a relatively lower power consumption.