• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2192-2195
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• 2003

This parer proposes a power-line phase measurement algorithm which is based on the recursive implementation of sliding-DFT. Usage of the single DFT coefficient in the conventional sliding-DFT based power-line phase measurement brings a significant error propagation when implemented in hardware with finite word-length arithmetic operations. The proposed algorithm utilizes all the N-point DFT coefficients in the recursion. Performance degradation caused by the finite word- length implementation of the algorithm is analyzed and verified with computer simulations. The robustness of the proposed phase measurement algorithm against the erroneous implementation is also confirmed by the performance analysis and simulation.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.863-866
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• 2005

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• Transactions of the Korean Society of Automotive Engineers
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• v.2 no.4
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• pp.80-90
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• 1994

Basic constraint equations derived from orthogonality conditions between a pair of body-fixed vectors and a body-fixed vector or a vector between two bodies are reformulated by using relative coordinate kinematics between two adjacent reference frames. Arithmetic numbers of operations required to compute derivatives of the constraint equations are drastically reduced. A mixed formulation of relative and cartesian coordinates is developed to further simplify derivatives of the constraints. Advantages and disadvantages of the new formulation are discussed. Possible singularity problem of para llelism constraints is resolved by introducing an extra generalized coordinate. Kinematic analysis of a McPherson strut suspension system are carried out to illustrate use and efficiency of the new formulation.

• Journal of the Korean Society of Industry Convergence
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• v.17 no.3
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• pp.184-193
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• 2014

Machine vision systems is applied for various industries such as optimize your spending, automate your production and maximize your efficiency. This research is effective for most optimal light condition of machine vision that technology was applied bald outside human visual acuity. Image processing converts a target image captured by a CCD camera into a digital signal and then performs various arithmetic operations on the signal to extract the characteristics of the target, such as points, lines, circles, area and length. The mathematical concepts of convolution and the kernel matrix are used to apply filters to signals, to perform functions such as extracting edges and reducing unwanted noise. This research analyze and compares matching ratio with reference image and search for optimal lighting condition in accuracy that user wants coming input image according to brightness change of lighting.

• Proceedings of the Korean Information Science Society Conference
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• 2011.06d
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• pp.111-114
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• 2011

PRBAC모델은 RBAC(Role Based Access Control) 모델에 조건(condition), 목적(purpose), 의무(obligation)개념을 포함시킴으로써 프라이버시를 강화한 모델이다. 그러나 조건 표현 내에 산술연산 기능을 지원하지 못한다고 알려져 있다. 본 논문에서는, 프라이버시를 보호하는 쇼핑몰 홈페이지를 구현하는 것을 목표로, 이 중 PRBAC모델을 XML로 구현하고 이를 Java와 연동함으로써 산술연산 기능을 지원하는 방안과, 홈페이지 코드와 데이터베이스를 연결하는 부분에 대한 연구결과를 소개한다.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.333-336
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• 2000

We discuss the direct methods (Gauss-Jordan and Gaussian eliminations) to solve linear systems on distributed memory parallel computers. It will be shown that the so-called row-cyclic storage gives rise to the best performance among the standard three (row-cyclic, column-cyclic and cyclic-cyclic) data storages. We also show that Gauss-Jordan elimination, rather than Gaussian elimination, is highly efficient for the direct solution of linear systems in parallel processing, though Gauss-Jordan elimination requires a larger number of arithmetic operations than Gaussian elimination. Numerical experiment is performed on HITACHI SR12201 with the standard libraries MPI and BLAS.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.10a
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• pp.76-78
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• 2003

We have designed and tested an RSFQ (Rapid Single Flux Quantum) NDRO (Non Destructive Read Out) circuit for the development of a high speed superconducting ALU (Arithmetic Logic Unit). When designing the NDRO circuit, we used Julia, XIC and Lmeter for the circuit simulations and layouts. We obtained the simulation margins of larger than $\pm$25％. For the tests of NDRO operations, we attached the three DC/SFQ circuits and two SFQ/DC circuits to the NDRO circuit. In tests, we used an input frequency of 1 KHz to generate SFQ Pulses from DC/SFQ circuit. We measured the operation bias margin of NDRO to be $\pm$15％. The circuit was measured at the liquid helium temperature.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.711-714
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• 2000

In this paper, we propose a high-speed multiplier-free realization using ROM’s to store the results of coefficient scalings in Combination With higher signal rate and pipelined operations. We show that hardware multipliers are not needed. By varying some parameters, the proposed structure provides various combinations of hardware and clock speed (or through-put). An example is given comparing the proposed realization with the distributed arithmetic (DA) realization. Results show that With Proper Choices of the Parameters the proposed structure achieves a faster processing speed with less hardware, as compared to the DA realization.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1236-1248
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• 1991

A new fast algorithm for computing the discrete cosine transform(DCT) Is developed decomposing N-point DCT into an N /2-point DCT and two N /4 point transforms(transpose of an N /4-point DCT. TN/t'and)It has an important characteristic that in this method, the roundoff noise power for a fixed point arithmetic can be reduced significantly with respect to the wellknown fast algorithms of Lee and Chen. since most coefficients for multiplication are distributed at the nodes close to the output and far from the input in the signal flow graph In addition, it also shows three other versions of factorization of DCT matrix with the same number of operations but with the different distributions of multiplication coefficients.

• Current Optics and Photonics
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• v.2 no.5
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• pp.400-406
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• 2018

The Semiconductor Optical Amplifier (SOA)-based Mach-Zehnder interferometer is a major contributor in all-optical digital processing and optical computation. Optical tree architecture provides one of the new, alternative schemes for integrated all-optical arithmetic and logical operations. In this paper, we propose an all-optical 3-bit integrated parity generator and checker using SOA-MZI-based optical tree architecture. The proposed scheme, able to process input signals at a desired operating wavelength, has been characterized using RZ-modulated signals at 10 Gbps. The maximum extinction ratios achieved at the output of the parity generator and checker are 10 dB and 8 dB respectively.