• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.913-916
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• 2009

This paper describes a hardware design of hash processor which implements HAS-160 algorithm adopted as a Korean standard. To achieve a high-speed operation with small-area, the arithmetic operation is implemented using a hybrid structure of 5:3 and 3:2 carry-save adders and a carry-select adder. The HAS-160 processor synthesized with $0.35-{\mu}m$ CMOS cell library has 17,600 gates. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency.

• The Journal of Information Technology
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• v.8 no.3
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• pp.1-10
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• 2005

Cosine and Sine function is widely used for the arithmetic, translation, object drawing, Simulation and etc. of Computer Graphics in Natural Science and Engineering. In general, Cordic Algorithm is effective method since it has relatively small size and simple architecture on trigonometric function generation. However profitably it has those merits, the problem of operation speed is occurred. In graphic display system, the operation result of object drawing is quantized and has the condition that is satisfied with rms error less than 1. So in this paper, the proposed generator is composed of partition operation at each ${\pi}/4$ and basic Cosine, Sine function generator in the range of $0{\sim}{\pi}/4$ using the lower order of Tayler's series in an acceptable error range, that enlarge the range of $0{\sim}2{\pi}$ according to a definition of the trigonometric function for the purpose of having a high speed Cosine, Sine function generation. And, division operator using code partition for divisor three is proposed, the proposed function generator has high speed operation, but it has the problems in the other application parts with accurate results, is need to increase the speed of the multiplication.

• Journal of Power Electronics
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• v.14 no.3
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• pp.507-518
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• 2014

This paper presents a new cascaded asymmetrical single phase multilevel converter with a lower number of power semiconductor switches and isolated DC sources. Therefore, the number of power electronic devices, converter losses, size, and cost are reduced. The proposed multilevel converter topology consists of two H-bridges connected in cascaded configuration. One H-bridge operates at a high frequency (high frequency inverter) and is capable of developing a two level output while the other H-bridge operates at the fundamental frequency (low frequency inverter) and is capable of developing a multilevel output. The addition of each power electronic switch to the low frequency inverter increases the number of levels by four. This paper also introduces a hybrid switching algorithm which uses very simple arithmetic and logical operations. The simplified hybrid switching algorithm is generalized for any number of levels. The proposed simplified switching algorithm is developed using a TMS320F2812 DSP board. The operation and performance of the proposed multilevel converter are verified by simulations using MATLAB/SIMULINK and experimental results.

• ETRI Journal
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• v.42 no.4
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• pp.596-607
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• 2020

Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)-based DSPs, scaling represents a performance bottleneck based on the complexity of intermodulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well-known moduli sets {2ⁿ - 1, 2ⁿ, 2ⁿ + 1} and {2ⁿ, 2ⁿ - 1, 2ⁿ⁺¹ - 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic-friendly moduli set {2^n+p, 2ⁿ - 1, 2ⁿ⁺¹ - 1}. The proposed algorithm yields high speed and energy-efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed-radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler.

• KIPS Transactions on Software and Data Engineering
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• v.10 no.4
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• pp.125-132
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• 2021

As the layers of artificial neural network deepens, and the dimension of data used as an input increases, there is a problem of high arithmetic operation requiring a lot of arithmetic operation at a high speed in the learning and recognition of the neural network (NN). Thus, this study proposes a data dimensionality reduction method to reduce the dimension of the input data in the NN. The proposed Line-segment Feature Analysis (LFA) algorithm applies a gradient-based edge detection algorithm using median filters to analyze the line-segment features of the objects existing in an image. Concerning the extracted edge image, the eigenvalues corresponding to eight kinds of line-segment are calculated, using 3×3 or 5×5-sized detection filters consisting of the coefficient values, including [0, 1, 2, 4, 8, 16, 32, 64, and 128]. Two one-dimensional 256-sized data are produced, accumulating the same response values from the eigenvalue calculated with each detection filter, and the two data elements are added up. Two LFA256 data are merged to produce 512-sized LAF512 data. For the performance evaluation of the proposed LFA algorithm to reduce the data dimension for the recognition of handwritten numbers, as a result of a comparative experiment, using the PCA technique and AlexNet model, LFA256 and LFA512 showed a recognition performance respectively of 98.7% and 99%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.715-722
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• 2010

This paper describes a hardware design of hash function processor which implements Korean Hash Algorithm Standard HAS-160. The HAS-160 processor compresses a message with arbitrary lengths into a hash code with a fixed length of 160-bit. To achieve high-speed operation with small-area, arithmetic operation for step-operation is implemented by using a hybrid structure of 5:3 and 3:2 carry-save adders and carry-select adder. It computes a 160-bit hash code from a message block of 512 bits in 82 clock cycles, and has 312 Mbps throughput at 50 MHz@3.3-V clock frequency. The designed HAS-160 processor is verified by FPGA implementation, and it has 17,600 gates on a layout area of about $1\;mm^2$ using a 0.35-${\mu}m$ CMOS cell library.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of Korea Multimedia Society
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• v.18 no.11
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• pp.1332-1341
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• 2015

This paper proposes a novel reversible secret sharing scheme using AES algorithm in encrypted images. In the proposed scheme, a role of the dealer is divided into an image provider and a data hider. The image provider encrypts the cover image with a shared secret key and sends it to the dealer. The dealer embeds the secret data into the encrypted image and transmits encrypted shadow images to the corresponding participants. We utilize Galois polynomial arithmetic operation over 2⁸ and the coefficient of the higher-order term is fixed to one in order to prevent the overflow. In experimental results, we demonstrate that the PSNR is sustained close to 44dB and the embedding capacity is 524,288 bits.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.18 no.1
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• pp.79-84
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• 2018

This paper relates with the performance improvement of SE-MMA (Signed Error-Multiple Modulus Algorithm) adaptive equalization algorithm that is used for the reduction of the intersymbol interference due to the distortion which occurs in the communication channel for the transmission of 16-QAM nonconstant modulus signal.. In the conventional MMA, the fixed modulus value that is second order statistics of transmitting signal were used, and the SE-MMA was introduced in order to the simplification of the algorithm's arithmetic operation. The SE-MMA have a fast convergence speed than MMA, but it has a problem of degradation of equalization performance in the steady state due to the arithmetic simplification. In this paper, we propose the new algorithm AV-SE-MMA (Adaptively Varying-SE-MMA) that uses the adaptive varying modulus in order to obtain the error signal for updating the adaptive equalizer coefficient, and its equalization performance were confirmed by simulation. In this paper, the performance of SE-MMA and proposed algorithm were compared, and the equalizer output signal constellation, residual isi, MSE and SER in order to confirm the robustness of noise were used as performace index. As a result of performance comparison, the AV-SE-MMA has better performance in output signal constellation, residual isi and MD compared to the SE-MMA, but it was confirmed that the AV-SE-MMA has similar in the SER performance that means the robustness to the noise.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).