Experimental Validation of a Cascaded Single Phase H-Bridge Inverter with a Simplified Switching Algorithm

Abstract

This paper presents a new cascaded asymmetrical single phase multilevel converter with a lower number of power semiconductor switches and isolated DC sources. Therefore, the number of power electronic devices, converter losses, size, and cost are reduced. The proposed multilevel converter topology consists of two H-bridges connected in cascaded configuration. One H-bridge operates at a high frequency (high frequency inverter) and is capable of developing a two level output while the other H-bridge operates at the fundamental frequency (low frequency inverter) and is capable of developing a multilevel output. The addition of each power electronic switch to the low frequency inverter increases the number of levels by four. This paper also introduces a hybrid switching algorithm which uses very simple arithmetic and logical operations. The simplified hybrid switching algorithm is generalized for any number of levels. The proposed simplified switching algorithm is developed using a TMS320F2812 DSP board. The operation and performance of the proposed multilevel converter are verified by simulations using MATLAB/SIMULINK and experimental results.

I. INTRODUCTION

In recent years, the demand for green energy has been heading towards a huge distribution of electric generators driven by solar, wind, fuel cell, hydro, and other renewable energy sources. This tendency will extend throughout the subsequent years because the power produced by renewable sources is expected to satisfy 30% and 60% of the comprehensive needs in the years 2020 and 2050, respectively.

An important consequence of this circumstance is the need to replace the present electric power system, which consists of a low number of very high power ac generators, to a scattered one, which has a huge number of small to medium power ac and dc generators supplied by renewable energy sources connected to the grid through power electronic converters.

This new development introduces various political, financial, and technical challenges because it alters the way in which the electrical energy resources (generation, transmission and distribution) are designed and controlled. From the technical perspective, the use of power electronic converters creates new issues, including increased complexity, increased power losses, electromagnetic interferences (EMIs) and reduced power quality, thus reducing the overall efficiency and stability.

Hence, numerous researchers have put their efforts in proposing new inverter configurations or in altering the existing ones, to improve the quality of the power available at the inverter terminals. Among the various inverter topologies, pulse width modulated (PWM) multilevel inverters (MLIs) are very popular [1]. In the beginning, they were used mainly in high-voltage high-power applications since the applied voltage is distributed among a number of cascaded power devices, thus overcoming their voltage limits [2]-[7]. As their output voltage is staircase in nature, they are better than two-level PWM inverters in terms of total harmonic distortion (THD), without the use of hefty, costly and dissipative passive filters. Therefore, in recent times, MLIs have been recommended in the field of renewable energies, including photovoltaic (PV) and fuel cell (FC) generators [8]-[10].

There are three fundamental MLI configurations: neutral point clamped, flying capacitor MLIs, and cascaded H-bridge MLIs (CHB-MLI). The neutral point clamped and flying capacitor MLIs require only one DC source to develop a multilevel output whereas the CHB-MLI requires more than one isolated DC source. The CHB-MLI cannot be used when a single dc source is available. However, this drawback becomes a very attractive feature in the case of PV or FC systems, because solar cells or fuel cell stacks can be assembled in a number of separate generators.

A significant problem in multilevel converter design is the complexity of their control and pulse width modulator. Many authors have proposed diverse solutions (e.g., [11]-[35]). Generally if the number of output voltage levels is increased, then the number of power electronic devices and the number of isolated DC sources are also increased. This makes a CHB inverter even more complex.

In the case of the converters for PV and FC generators, another important issue is the achievement of maximum power point tracking (MPPT). DC-DC converters are mandatory for each of the isolated DC sources in a PV or FC application. These converters adjust the variable or low quality output voltage of PV or FC stacks. In addition, the power output of PV and FC stacks has to be maximized as it depends on ecological factors. Therefore, in order to track the maximum power point of the photovoltaic string or fuel cell stacks, additional voltage and current sensors are required for each DC-DC converter. These additional sensors further increase the system complexity.

In this paper, a multilevel inverter with a minimum number of power electronic switching devices is proposed. It is a modified version of a multilevel inverter using the series/parallel conversion of DC sources (MLISPC) developed in [15]. In the proposed multilevel inverter, an auxiliary circuit comprising of four diodes and a switch is introduced instead of the series/parallel switches of the inverter found in the MLISPC. However, only two isolated voltage sources are needed to output the same number of voltage levels when compared to conventional CHB inverters and the MLISPC.

The number of switching devices used and the harmonics of the output voltage waveform for the proposed inverter are reduced when compared to the conventional methods. The proposed multilevel inverter topology can be extended for the application of grid connected photo voltaic systems, hybrid electric vehicles, etc. Theoretical analysis, numerical simulations and experimental results are presented to demonstrate the validity of the proposed cascaded asymmetrical single phase multilevel converter.

Section II describes the circuit topology of the proposed multilevel inverter. In Section III, the generalized PWM modulation technique of the proposed inverter is explained. In Section IV, the converter losses are discussed. Sections V and VI validate the simulation and experimental results.

 

II. CIRCUIT TOPOLOGY

Fig. 1 shows the circuit configuration of the proposed cascaded H-bridge multilevel inverter with two H-bridge inverters connected in cascade (upper and lower H-bridge inverters). The DC voltage sources vdco - vdcn may either be independent or dependent on each other. The magnitude of each voltage source in the lower H-bridge is two times the magnitude of the upper H-bridge voltage source (i.e. = vdcn/vdc0 = 2). The lower H-bridge of the MLISPC is replaced with the one developed in [13], [14], [16], [17]. As shown in Fig. 1, in the lower H-bridge, an auxiliary circuit comprising of four diodes and a switch placed between two DC sources.

Fig. 1.Proposed cascaded H-bridge multilevel inverter.

Using the proposed circuit configuration, the lower H-bridge inverter outputs Vlow = 2n+1 levels, while the upper H-bridge outputs Vup = vdc0. The proposed inverter outputs 4n + 3 levels by Vlow + Vup or Vlow-Vup. Here, n is the number of capacitor sources in the lower H-bridge inverter. Fig. 2 shows the lower H-bridge inverter with two capacitor sources, which outputs five levels. The switching states of the five level inverter (lower H-bridge) are shown in the Table I.

Fig. 2.Operation of lower inverter.

TABLE ISWITCHING STATES OF LOWER H-BRIDGE INVERTER

Table II gives the complete switching states and the derived output of the proposed multilevel inverter to generate 11 levels. The modes of operation indicated in Table II correspond to the modes pointed out in Fig. 4. In Table II, the symbol ↔ indicates that the voltage level switches between two extremes.

TABLE IISWITCHING STATES OF PROPOSED INVERTER

Fig. 3.Modulation strategy of the proposed inverter.

Fig. 4.Reference waveform generation for an 11 level inverter (upper bridge).

A. Capacitor Voltage Balancing

Since the main application of the proposed inverter is fed from a photovoltaic (PV) array or fuel cell (FC) stacks, DC-DC boost converters are required to boost the low output voltage of the PV panels or FC stacks. Hence, two boost converters are used, one for the upper H-bridge inverter and the other for the lower H-bridge inverter. For the lower inverter, the Multi Output Boost (MOB) DC-DC converter proposed in [36] is used. One of the most interesting applications of this MOB DC-DC converter is the boosting and regulation of the low and variable output voltage of renewable energy for the DC link of grid connected systems, based on multilevel inverters [2]. Hence, the MOB DC-DC converter serves the following two purposes:

The proposed inverter, fed from a multi output DC-DC converter, is shown in Fig 5.

Fig. 5.Proposed cascaded H-Bridge multilevel inverter fed from multi output boost converter.

 

III. GENERALIZED PWM MODULATION TECHNIQUE

This section determines the switching function to get the output of the eleven levels in the proposed inverter. The same procedure can be extended to derive the switching function of an N level inverter. A hybrid PWM modulation technique is used to generate the PWM switching signals [19]. Fig 3 shows the PWM Modulation scheme of the proposed 11 level inverter. The total reference waveform is generated as shown in Fig. 4 (a) and defined in (1).

Where A is the peak value of the reference waveform. (A = 5 for 11 level inverter). The above equation is scaled down as given in (2).

The reference waveform for the upper inverter is generated by using the following expressions:

Equation (3) is a simple zero crossing detector, while (4) gives the expected output of the lower H-bridge inverter (Vlow) and (5) is a mathematical representation of the upper H-bridge inverter reference waveform. The output of equations (4) and (5) for the 11 level inverter are shown in Fig. 4(b) and Fig. 4(c). The above equations can be used for higher inverter levels by simply changing the value of A. For example, A = 7 for 15 levels, A = 9 for 19 levels, A = 11 for 23 levels just to mention a few. In order to generate the switching patterns for the lower inverter, the first step is to generate the reference waveform for the lower inverter.

The next step is to split the above reference wave into many signals of Ry.

Where y = 1 to X. After dividing the reference of the lower inverter into many sub-signals, it is necessary to find out the number of auxiliary switches required for an N level inverter.

The main switches of the lower inverter are switched as per the equations given below:

Where y = X, + denotes the logical OR operation and * denotes the multiplication of the signals. The auxiliary switches of the lower inverter can be switched as per the algorithm given below.

1) Step 1: Form a set:

2) Step 2: Write the permutation P on R as given below:

3) Step 3: Remove the last column in the above permutation P1 and rewrite as:

4) Step 4: From the above equation, it is very easy to derive the switching pulses for all of the auxiliary switches of the N level inverter. The first and last columns of the above matrix are responsible for developing the switching patterns for the first and last auxiliary switches and the equations for AS1 and ASn are:

Where ⊕ denotes the XOR operation. Similarly, the 2nd column from the first and 2nd columns from the last of the permutation matrix P1 are responsible for developing the switching patterns of AS2 and AS(n-1) and the equations are:

The above procedure can be repeated to generate the switching patterns for any pair of auxiliary switches based on the following cases.

CASE I (If P1 contains an odd number of columns): Sometimes as in the case of a 19 level inverter, when X = 4, the number of R signals available will be four (i.e.) R1; R2; R3 and R4. The number of auxiliary switches in the 19 level inverter will be three. As per the algorithm, the permutation P1 will be:

The first and last columns of the above P1 will be responsible for constructing the switching patterns for AS1 and AS3. However, for developing the switching pattern for AS2, only the center column of the permutation P1 should be used. The switching pattern for AS2 can be developed as:

The possibility of CASE I is also valid for N = 11, 19, 27, 35, 43....

CASE II (If P1 contains an even number of columns): In the case of a 23 level inverter, when X = 5, the number of R signals available will be five (i.e.) R1, R2, R3, R4 and R5 whereas the number of auxiliary switches in the 23 Level inverter will be four. As per the algorithm, the permutation P1 will be:

The first and last columns of the above P1 will be responsible for constructing the switching patterns for AS1 and AS4, and the 2nd and 3rd columns are used for developing the switching pattern for AS2 and AS3. Columns 2 and 3 have only three unique R signals (i.e.) R2, R3 and R4 to develop the switching patterns for AS2 and AS3.

The possibility of CASE II is also valid for N = 15, 23,31, 39, 47 etc. The modulation index Ma of the proposed N level inverter is defined as:

Where

Where Apr represents the peak value of the modulating or reference wave and Apc represents the peak to peak value of the carrier (triangular) wave. The main switches MS1 and MS3 are switched by comparing the reference waveform R01 with the carrier wave. As a result, the voltage Vxz between points x and z in Fig. 1 appears as shown in Fig. 3. The main switches MS2 and MS4 are switched by comparing the reference waveform R02 with the carrier wave. As a result, the voltage Vyz between points y and z in Fig. 1 appears as shown in Fig. 3. The main switches of the lower bridge inverter MS5 - MS8 are switched as per equations (10)-(13) and auxiliary switch AS1 is switched as per the above proposed algorithm, as shown in Fig. 3. The proposed generalized algorithm is very simple since it makes use of simple logical operations.

 

IV. CONVERTER LOSSES

The average switching power loss Psloss in the switch during the transition of switch is given by:

Where tc(on) and tc(off) are the turn on and turn off cross over intervals, respectively; VDS is the voltage across the switch and Idc is the current which flows through the switch. For the sake of clarity, the proposed topology with 15 levels is compared with familiar, similar topologies. For simplification, the proposed topology and the well-known inverter topologies are assumed to operate at the same turn-on and turn-off crossover intervals and at the same Idc. Then, the average switching power loss Psloss is proportional to VDS and fs.

The number of primary devices required for generating 15 levels in the proposed inverter is 10 and the voltage across these switches is VDC for the upper H-bridge switches (4 numbers), 6VDC for the lower H-bridge switches (4 numbers) and 4VDC for the auxiliary switches (2 numbers). The upper H-bridge inverter switches at a high frequency fs, the lower H-bridge inverter switches at the fundamental frequency fm and the auxiliary devices switch twice at the fundamental frequency (2fm). Therefore, the switching losses of the proposed inverter can be written as:

Similarly, the number of primary devices required for generating 15 levels in the MLISPC inverter is 14 and the voltage across these switches is VDC for the upper H-bridge switches (4numbers), 6VDC for the lower H-bridge switches (4 numbers) and 2VDC for the series/parallel switches (6 numbers). The upper H-bridge inverter switches at a high frequency fs, the lower H-bridge inverter switches at the fundamental frequency fm and the series/parallel switches switch twice at the fundamental frequency (2fm). Therefore, the switching losses of the proposed inverter can be obtained as:

Likewise, for conventional symmetrical CHB inverters, the switching losses can be calculated as:

For an asymmetrical cascaded H bridge inverter with 1:2:4 configurations, the switching losses can be obtained as:

Since fs ≫ fm and from equations (27)-(32), it is evident that among the various familiar topologies, the proposed topology has the lowest switching losses when compared to the other topologies. In the proposed inverter, at any point in time, the number of switches in conduction is only 4 (2 from the upper inverter and 2 from the lower inverter). Therefore, the conduction losses Pcloss of the proposed inverter are:

Where RON is the internal resistance of the switching device and I is the current flowing into the devices. In the case of the MLISPC topology, the number of conducting devices increases as the number of levels increases. This in turn, increases the conduction losses. The same is true for all of the well-known topologies. Hence, the conduction losses are lower in the case of the proposed topology when compared to the MLISPC, the conventional symmetrical CHB and asymmetrical CHB inverters.

 

V. SIMULATION RESULTS

To validate the proposed inverter topology, simulations are carried out for the proposed inverter in Matlab/Simulink. The algorithm discussed in Section III is implemented in the simulations up to 43 levels and it can be extended to any required level. The conditions set for simulation and experiment are same. Table III gives the simulation parameters for 11, 15 and 43 level inverters. The upper inverter is operated at a high switching rate that is equivalent to the carrier frequency (i.e. 10 kHz), while the lower inverter is operated at a low frequency (nearly equal to the fundamental frequency i.e. 50Hz). Fig. 6 shows the simulation results for the load voltage of the 11 level inverter together with the upper and lower inverter voltages for a modulation index of Ma= 1. When the modulation index is reduced from 1, the number of voltage levels at the load also decreases. Fig. 7 shows the output across the load and the upper and lower inverters for the modulation index Ma= 0.8 (i.e. when the value of A = 4). From Fig. 6 and Fig.7 it is observed that when the modulation index is reduced from 1 to 0.8, the output voltage across the load has only nine levels. Any further reduction in the modulation index will reduce the number of voltage levels at the load end. For example, when Ma = 0.6 i.e. A = 3 the number of levels obtained at the load voltage is seven, when Ma = 0.4 i.e. A = 2 the voltage level at the load becomes five and so on. Fig. 8 shows the resultant waveforms of a 15 level inverter along with the upper and lower inverter waveforms for a modulation index of Ma= 1 (i.e. A = 7). Any further decrease in the value of A leads to a reduction in the output voltage levels. For example, when A =5, it generates an 11 level output as shown in Fig. 6. Fig. 9 shows the simulation results of a 43 level inverter along with the upper and lower inverters, in which the load voltage is very close to sinusoidal. Table IV gives the details of the total harmonic distortion at the load voltage and current for various output voltage levels.

TABLE IIISIMULATION PARAMETERS

Fig. 6.(a) Voltage across the load (11 Levels). (b) Voltage across the upper inverter Vup. (c) Voltage across the lower inverter Vlow. (d) Load Current waveform for modulation index Ma=1.

Fig. 7.(a) Voltage across the load (9 Levels). (b) Voltage across the upper inverter Vup. (c) Voltage across the lower inverter Vlow. (d) Load Current waveform for modulation index Ma=0.8.

Fig. 8.(a) Voltage across the load (15 Levels). (b) Voltage across the upper inverter Vup. (c) Voltage across the lower inverter Vlow. (d) Load Current waveform for modulation index Ma=1.

Fig. 9.(a) Voltage across the load (43 Levels A = 21). (b) Voltage across the upper inverter Vup. (c) Voltage across the lower inverter Vlow. (d) Load Current waveform for modulation index Ma=1.

TABLE IVTHD FOR VOLTAGE AND CURRENT FOR VARIOUS LEVELS

 

VI. EXPERIMENTAL RESULTS

Fig. 10 shows a schematic diagram for the hardware setup of the proposed inverter, developed in the laboratory, for 15 levels. The upper and lower inverters consist of MKI 80-06T6K series IGBTs. The auxiliary switch used in the lower inverter is a FIO50-12BD bidirectional device. The gate driving signal is developed by using a TMS320F2812 Texas instruments DSP. The programs for the TMS320F2812 DSP are composed with code composer studio and Matlab/Simulink. Fig. 11 shows the experimental results of a 15 level inverter with a modulation index of 1 and a switching frequency of 10 KHz. The prototype inverter is made to drive an RL load with the values of R and L indicated in Table III.

Fig. 10.Schematic diagram for the hardware Setup of the proposed inverter (15 Levels).

Fig. 11.Hardware results (a)Voltage across the lower inverter Vlow (b)Voltage across the upper inverter Vup (c) Voltage across the load (15 Levels) (d) Load Current waveform for modulation index Ma=1.

Fig. 12 shows the hardware results of a 15 level inverter with and without a filter. The values of the LC filter used in the hardware prototype are similar to those of the simulation environment. A study very similar to the simulation is done in the hardware prototype for various modulation indices. Fig. 13 shows the experimental results of a 15 level inverter when the modulation index is reduced to 0.7 (i.e. when A = 5), which leads to an 11 level output at the load terminals.

Fig. 12.Hardware results (a) Voltage across the load (15 Levels) with out filter (b) With LC filter.

Fig. 13.Hardware results When 15 level inverter is driven by Ma=0.7.(a)Voltage across the upper inverter Vup (b) Voltage across the lower inverter Vlow (c) Voltage across the load (11 Levels) (d) Load Current waveform.

Fig. 13 includes the waveforms of the upper and lower inverter along with the load current waveform for Ma = 0.7. Fig. 14 shows the hardware results of a 15 level inverter when driven by a modulation index of 0.4, which leads to a 7 level output at the load terminals. Fig. 15 presents the total harmonic distortion content of the voltage, current and power obtained from the hardware prototype along with the load voltage for a 15 level inverter when driven with a modulation index of 0.4, which leads to a 7 level output. As indicated in Table IV, the THD values obtained from the simulation and the results obtained from the hardware prototype match well for a 7 level inverter without a filter. In order to study the performance of the proposed inverter, the inductive load is varied over a wide range. Fig. 16 and Fig. 17 show the load voltage and current waveforms of the proposed inverter for various power factors. It is evident from the load profile waveforms that the proposed inverter is also capable of supplying power to a highly inductive load.

Fig. 14.Hardware results When 15 level inverter is driven by Ma=0.4.(a)Voltage across the load (7 Levels) (b) Voltage across the lower inverter Vlow(c) Voltage across the upper inverter Vup (d) Load Current waveform

Fig. 15.Harmonic Spectrum of 15 level inverter when drive by Ma=0.4.(a)Numerical Values of Voltage, Current and Power THD (b)Inverter load voltage (7 Level output).

Fig. 16.Load voltage and current waveform for power factor of 0.9837.

Fig. 17.Load voltage and current waveform for power factor of 0.6198.

In order to validate the proposed multilevel inverter fed from a multi output DC-DC boost converter, a step change in the reference values of the lower DC link capacitors were given at 0.5 secs (i.e. a change from 50 Volts to 100 Volts). Similarly a step change in the upper boost converter is given at 0.5 secs (i.e. from 25 Volts to 50 Volts) in order to maintain the ratio between the lower and upper inverter DC link voltages as two. Fig 18 shows the experimental waveforms of the upper and lower capacitor voltages due to a step change in their reference values (i.e. the upper capacitor voltage is changed from 25 Volts to 50 Volts and the lower capacitor voltages are changed from 50Volts to 100 Volts). Fig 19 shows the corresponding changes in the upper inverter and lower inverter voltages along with the load voltage.

Fig. 18.Step response in Capacitor voltages of lower inverter along with load voltageobtained from the simulation and the results obtained from thehardware prototype match well for a 7 level inverter withoutfilter.

Fig. 19.Step response in capacitor voltages of upper and lower inverter along with upper, lower and load voltage waveform.

 

VII. CONCLUSIONS

Multilevel inverters offer enhanced output waveforms with a minimum of THD. This paper presents a novel single phase multilevel inverter with reduced switching devices and isolated DC sources. Simulations are carried out in MATLAB/Simulink and the proposed inverter is implemented in real time using a DSP board. A generalized switching algorithm which can be used for any number of levels is also presented. The performance of the suggested novel multilevel inverter is investigated in detail. Modulation waveforms and harmonic analyses are presented for various values of the modulation indices. By properly adjusting the modulation index, the required number of levels for the inverter output voltage can be achieved. The simulation and experimental results match perfectly with each other. The proposed inverter system offers the advantage of a reduced number of switching devices and isolated DC sources when compared to the conventional CHB and MLISCP for the same number of output levels. In addition, the high frequency switching devices are operated at a low voltage and the low frequency devices are operated at a high voltage. Thus, it can be concluded that the proposed novel multilevel inverter can be used for medium and high power applications.