• ETRI Journal
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• 제27권5호
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

• 대한조선학회논문집
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• 제44권2호
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• pp.55-63
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• 2007

Fins are widely used for roll stabilization of car ferries and passenger ships as well as high performance naval ships. In the present study, model experiments and numerical simulations are performed to investigate the influence of tail blades on the performance of a fin stabilizer for various angles of attack. It is found that a considerable improvement in performance of the fin stabilizer is achieved with adoption of the tail blades. The results can be utilized for the design of a high-lift control surfaces including fin stabilizers.

• 한국산업정보학회논문지
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• 제8권3호
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• pp.12-18
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• 2003

A web crawler is used widely in a variety of Internet applications such as search engines. As the Internet continues to grow, high performance web crawlers become more essential. Crawl scheduling which manages the allocation of web pages to each process for downloading documents is one of the important issues. In this paper, we identify issues that are important and challenging in the crawl scheduling. To address the issues, we propose a dynamic owl scheduling framework and subsequently a system architecture for a web crawler subject to the framework. This paper presents the architecture of a web crawler with dynamic scheduling support. The result of our preliminary performance evaluation made to the proposed crawler architecture is also presented.

• 대한산업공학회지
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• 제39권1호
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• pp.1-9
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• 2013

The current manufacturers have generated tremendous amount of digitized product data to efficiently share and exchange it with other stakeholders or various software systems for product development. The digitized product data is a valuable asset for manufacturers, and has a potential to support high level strategic decision makings needed at many stages in product development. However, the lack of studies on extraction of key performance indicators(KPIs) from product data management(PDM) databases has prohibited manufacturers to use the product data to support the decision makings. Therefore this paper examines a possibility of an architecture that supports KPIs for evaluation of product development performances, by applying multidimensional product data model and on-line analytic processing(OLAP) to operational databases of product data management. To validate the architecture, the paper provides a prototype product data management system and OLAP applications that implement the multidimensional product data model and analytic processing.

• Earthquakes and Structures
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• 제10권5호
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• pp.1111-1123
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• 2016

To study seismic performance of steel frame-bent structure, one specimen with one-tenth scale, three-bay, and five-story was tested under reversed cyclic lateral load. The entire loading process and failure mode were observed, and the seismic performance indexes including hysteretic loops, skeleton curve, ductility, load bearing capacity, drift ratio, energy dissipation capacity and stiffness degradation were analyzed. The results show that the steel frame-bent structure has good seismic performance. And the ductility and the energy dissipation capacity were good, the hysteresis loops were in spindle shape, which shape were full and had larger area. The ultimate elastic-plastic drift ratio is larger than the limit value specified by seismic code, showing the high capacity of collapse resistance. It can be helpful to design this kind of structure in high-risk seismic zone.

• 한국시뮬레이션학회논문지
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• 제8권4호
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• pp.1-8
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• 1999

This paper proposes an ATM switch architecture called Output Queued Batcher-Banyan switch (OQBBS). It consists of a Sorting Module, Expanding Module, and Output Queueing Modules. The principles of channel grouping and output queueing are used to increase the maximum throughput of an ATM switch. One distinctive feature of the OQBBS is that multiple cells can be simultaneously delivered to their desired output. The switch architecture is shown to be modular and easily expandable. The performance of the OQBBS in terms of throughput, cell delays, and cell loss rate under uniform random traffic condition is evaluated by computer simulation. The throughput and the average cell delay are close to the ideal performance behavior of a fully connected output queued crossbar switch. It is also shown that the OQBBS meets the cell loss probability requirement of $10^{-6}$.

• IEIE Transactions on Smart Processing and Computing
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• 제3권6호
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• pp.353-357
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• 2014

This paper, presents an efficient hardware architecture of high performance SVC(Scalable Video Coding). This platform uses dedicated hardware architecture to improve its performance. The architecture was prototyped in Verilog HDL and synthesized using the Synopsys Design Compiler with a 65nm standard cell library. At a clock frequency of 266MHz, This platform contains 2,500,000 logic gates and 750,000 memory gates. The performance of the platform is indicated by 30 frames/s of the SVC encoder Full HD($1920{\times}1080$), HD($1280{\times}720$), and D1($720{\times}480$) at 266MHz.

• 한국태양에너지학회 논문집
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• 제25권2호
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• pp.71-79
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• 2005

In this study, the ventilation performance of mechanical ventilation system in apartment House was analyzed through model test according to characteristics of air-vent. Then adequate interval of air-vent was suggested using computer simulation which will create comfort environment through improvement of ventilation performance in apartment house. The result of experiment with separation plate to prevent mixture of contaminated exhaust air with fresh supply air, the ventilation efficiency improved about 10%. The result of simulation with horizontal location of exterior air-vent, contaminated exhaust air is mixed regardless of interval variation. Consequently, mixture of the exhaust air can be prevented through locating the supply air vent on the top side and exhaust air vent on the lower side.

• IEIE Transactions on Smart Processing and Computing
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• 제4권2호
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• pp.78-82
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• 2015

General-purpose graphics processing units (GPGPUs) provide tremendous computational and processing power. Despite the latency hiding mechanism, a GPU architecture requires high memory bandwidth and lower latency between computational units and the memory system. For this reason, the current GPU architecture has private L1 caches in each core and a shared L2 cache to increase performance by reducing memory latency. But in some cases, this CPU-like cache design is not suitable for GPGPUs. In this paper, we analyze detailed cache performance related to GPGPU application characteristics, and suggest technical alternatives for the GPGPU architecture as future work.

• 전기학회논문지
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• 제62권2호
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• pp.252-256
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• 2013

In order to overcome the complexity and performance limit problems of superscalar processors, the multi-core architecture has been prevalent recently. Usually, the number of cores mostly used for the multi-core processor architecture ranges from 2 to 16. However in the near future, more than 32-cores are likely to be utilized, which is called as many-core processor architecture. Using SPEC 2000 benchmarks as input, the trace-driven simulation has been performed for the 32 to 1024 many-core architectures extensively. For 1024-cores, the average performance scores 15.7 IPC, but the performance increase rate is saturated.