1 |
T. Ungerer, B. Robic, and J. Silk, "Multithreaded Processors," The Computer Journal, Vol. 45, No. 3, 2002
|
2 |
D. Pham et. al, "The Design and Implementation of a First-Generation CELL processor," ISSCC 2005.
|
3 |
D. Genbrugge and L. Eeckhout, "Chip Multiprocessor Design Space Exploration through Statistical Simulation," IEEE Transactions on Computers 58(12), pp.1668-1681, Dec. 2009.
DOI
ScienceOn
|
4 |
A. Rico, A. Duran. F. Cabarcas, Y. Etsion, A. Ramirex, and M. Valero, "Trace-driven Simulation of Multithreaded Applications," ISPASS, 2011.
|
5 |
M. Frankilin, G. S. Sohi, "ARB: A Hardware Mechanism for Dynamic Reordering of Memory References," IEEE Transactions on Computers, Vol. 45, No. 5, May 1996.
|
6 |
T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, vol. 35, no. 2, pp. 59-67, Feb. 2002.
DOI
ScienceOn
|
7 |
T-Y. Yeh and Y. N. Patt, "Alternative Implementations of Two-Level Adaptive Branch Prediction," in Proceedings of the 19th International Symposium on Computer Architecture, pp.124-134, May 1992.
|
8 |
S. Biswas, et. al, "Multi-Execution : Multicore Caching for Data-Similar Executions," International Symposium on Computer Architecture, Jun. 2009.
|
9 |
M. Monchiero, et. al, "How to Simulate 1000 Cores," ACM SIGARCH Computer Architecture News archive, Vol. 37, Issue 2, May 2009, pp. 10-19
DOI
|
10 |
A. Ghosh, S. Devadas, K. Keutzer and J. White, "Estimation of Average Switching Activity in Combinational and Sequential Circuits," ACM/IEE Design Automation Conf., pp. 253-259, 1992.
|
11 |
P. K. Dubey, G. B. Adams III, and M. J. Flynn, "Instruction Window Size Trade-Offs and Characterization of Program Parallelism," IEEE Transactions on Computers, vol. 43, pp 431-442, Apr. 1994.
DOI
ScienceOn
|
12 |
D. E. Culler and J. P. Singh, "Parallel Computer Architecture," Morgan Kauffmann Publishers, Inc. Aug. 1998.
|
13 |
S. W. Keckler, K. Olukotun, and H. P. Hofsee, "Multicore Processors and Systems," Springer. 2009.
|