• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.5
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• pp.233-240
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• 2021

We propose a novel, highly accurate approximate multiplier using different types of inexact 4-2 compressors. The importance of low hardware costs leads us to develop approximate multiplication for error-resilient applications. Several rules are developed when selecting a topology for designing the proposed multiplier. Our highly accurate multiplier design considers the different error characteristics of adopted compressors, which achieves a good error distribution, including a low relative error of 0.02% in the 8-bit multiplication. Our analysis shows that the proposed multiplier significantly reduces power consumption and area by 45% and 26%, compared with the exact multiplier. Notably, a trade-off relationship between error characteristics and hardware costs can be achieved when considering those of existing highly accurate approximate multipliers. In the image blending, edge detection and image sharpening applications, the proposed 8-bit approximate multiplier shows better performance in terms of image quality metrics compared with other highly accurate approximate multipliers.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.4
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• pp.671-678
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• 2022

Approximate computing is an computational technique that is acceptable degree of inaccurate results of accurate results. Approximate multiplication is one of the approximate computing methods for high-performance and low-power computing. In this paper, we propose a high-density, low-power, and high-speed approximate multiplier using approximate 4-2 compressor and improved full adder. The approximate multiplier with approximate 4-2 compressor consists of three regions of the exact, approximate and constant correction regions, and we compared them by adjusting the size of region by applying an efficient partial product reduction. The proposed approximate multiplier was designed with Verilog HDL and was analyzed for area, power and delay time using Synopsys Design Compiler (DC) on a 25nm CMOS process. As a result of the experiment, the proposed multiplier reduced area by 10.47%, power by 26.11%, and delay time by 13% compared to the conventional approximate multiplier.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.1
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• pp.173-180
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• 2022

Approximate Computing is a promising method for designing hardware-efficient computing systems. Approximate multiplication is one of key operations used in approximate computing methods for high performance and low power computing. An approximate 4-2 compressor can implement hardware-efficient circuits for approximate multiplication. In this paper, we propose an approximate multiplier with low area and low power characteristics. The proposed approximate multiplier architecture is segmented into three portions; an exact region, an approximate region, and a constant correction region. Partial product reduction in the approximation region are simplified using a new 4:2 approximate compressor, and the error due to approximation is compensated using a simple error correction scheme. Constant correction region uses a constant calculated with probabilistic analysis for reducing error. Experimental results of 8×8 multiplier show that the proposed design requires less area, and consumes less power than conventional 4-2 compressor-based approximate multiplier.

• ETRI Journal
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• v.43 no.4
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• pp.684-693
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• 2021

This paper presents a low-cost two-stage approximate multiplier for bfloat16 (brain floating-point) data processing. For cost-efficient approximate multiplication, the first stage implements Mitchell's algorithm that performs the approximate multiplication using only two adders. The second stage adopts the exact multiplication to compensate for the error from the first stage by multiplying error terms and adding its truncated result to the final output. In our design, the low-cost multiplications in both stages can reduce hardware costs significantly and provide low relative errors by compensating for the error from the first stage. We apply our approximate multiplier to the convolutional neural network (CNN) inferences, which shows small accuracy drops with well-known pre-trained models for the ImageNet database. Therefore, our design allows low-cost CNN inference systems with high test accuracy.

• Journal of the Korean Mathematical Society
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• v.54 no.4
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• pp.1063-1079
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• 2017

Two standard Bessel sequences in a Hilbert $C^*$-module are approximately duals if the distance (with respect to the norm) between the identity operator on the Hilbert $C^*$-module and the operator constructed by the composition of the synthesis and analysis operators of these Bessel sequences is strictly less than one. In this paper, we introduce (a, m)-approximate duality using the distance between the identity operator and the operator defined by multiplying the Bessel multiplier with symbol m by an element a in the center of the $C^*$-algebra. We show that approximate duals are special cases of (a, m)-approximate duals and we generalize some of the important results obtained for approximate duals to (a, m)-approximate duals. Especially we study perturbations of (a, m)-approximate duals and (a, m)-approximate duals of modular Riesz bases.

• ETRI Journal
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• v.39 no.2
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• pp.145-150
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• 2017

As wearable devices are powered by batteries, they need to consume as little energy as possible. To address this challenge, in this article, we propose a synergistic technique for energy-efficient approximate speech signal processing (ASSP) for wearable devices. More specifically, to enable the efficient trade-off between energy consumption and sound quality, we synergistically integrate an approximate multiplier and a successive approximate register analog-to-digital converter using our enhanced conversion algorithm. The proposed ASSP technique provides ~40% lower energy consumption with ~5% higher sound quality than a traditional one that optimizes only the bit width of SSP.

• Journal of IKEEE
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• v.26 no.4
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• pp.736-741
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• 2022

Lattice-based cryptography is the most practical post-quantum cryptography because it enjoys strong worst-case security, relatively efficient implementation, and simplicity. Ring learning with errors (R-LWE) is a public key encryption (PKE) method of lattice-based encryption (LBC), and the most important operation of R-LWE is the modular polynomial multiplication of rings. This paper proposes a method for optimizing modular multipliers based on approximate computing (AC) technology, targeting the medium-security parameter set of the R-LWE cryptosystem. First, as a simple way to implement complex logic, LUT is used to omit some of the approximate multiplication operations, and the 2's complement method is used to calculate the number of bits whose value is 1 when converting the value of the input data to binary. We propose a total of two methods to reduce the number of required adders by minimizing them. The proposed LUT-based modular multiplier reduced both speed and area by 9% compared to the existing R-LWE modular multiplier, and the modular multiplier using the 2's complement method reduced the area by 40% and improved the speed by 2%. appear. Finally, the area of the optimized modular multiplier with both of these methods applied was reduced by up to 43% compared to the previous one, and the speed was reduced by up to 10%.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.22 no.4
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• pp.811-825
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• 1998

An approximate line search is presented for dynamic response optimization with Augmented Lagrange Multiplier(ALM) method. This study empolys the approximate a augmented Lagrangian, which can improve the efficiency of the ALM method, while maintaining the global convergence of the ALM method. Although the approximate augmented Lagragian is composed of only the linearized cost and constraint functions, the quality of this approximation should be good since an approximate penalty term is found to have almost second-order accuracy near the optimum. Typical unconstrained optimization algorithms such as quasi-Newton and conjugate gradient methods are directly used to find exact search directions and a golden section method followed by a cubic polynomial approximation is empolyed for approximate line search since the approximate augmented Lagrangian is a nonlinear function of design variable vector. The numberical performance of the proposed approach is investigated by solving three typical dynamic response optimization problems and comparing the results with those in the literature. This comparison shows that the suggested approach is robust and efficient.

• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.5
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• pp.235-242
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• 2020

This paper analyzes the effect of reduced output width of the truncated logarithmic multiplication and application to inferences using convolutional neural networks (CNNs). For small hardware overhead, output width is reduced in the truncated Mitchell multiplier, so that fractional bits in multiplication output are minimized in error-resilient applications. This analysis shows that when reducing output width in the truncated Mitchell multiplier, even though worst-case relative error increases, average relative error can be kept small. When adopting 8 fractional bits in multiplication output in the evaluations, there is no significant performance degradation in target CNNs compared to existing exact and original Mitchell multipliers.

• Journal of Information Processing Systems
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• v.19 no.3
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• pp.377-384
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• 2023

The existence of abnormal breakpoint data leads to poor channel balance in wireless sensor networks (WSN). To enhance the communication quality of WSNs, a method for positioning abnormal breakpoint data in WSNs on the basis of signal reconstruction is studied. The WSN signal is collected using compressed sensing theory; the common part of the associated data set is mined by exchanging common information among the cluster head nodes, and the independent parts are updated within each cluster head node. To solve the non-convergence problem in the distributed computing, the approximate term is introduced into the optimization objective function to make the sub-optimization problem strictly convex. And the decompressed sensing signal reconstruction problem is addressed by the alternating direction multiplier method to realize the distributed signal reconstruction of WSNs. Based on the reconstructed WSN signal, the abnormal breakpoint data is located according to the characteristic information of the cross-power spectrum. The proposed method can accurately acquire and reconstruct the signal, reduce the bit error rate during signal transmission, and enhance the communication quality of the experimental object.