• Title/Summary/Keyword: Analysis of electronic circuits

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Suppression of Shrinkage Mismatch in Hetero-Laminates Between Different Functional LTCC Materials

  • Seung Kyu Jeon;Zeehoon Park;Hyo-Soon Shin;Dong-Hun Yeo;Sahn Nahm
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.36 no.2
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    • pp.151-157
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    • 2023
  • Integrating dielectric materials into LTCC is a convenient method to increase the integration density in electronic circuits. To enable co-firing of the high-k and low-k dielectric LTCC materials in a multi-material hetero-laminate, the shrinkage characteristics of both materials should be similar. Moreover, thermal expansion mismatch between materials during co-firing should be minimized. The alternating stacking of an LTCC with silica filler and that with calcium-zirconate filler was observed to examine the use of the same glass in different LTCCs to minimize the difference in shrinkage and thermal expansion coefficient. For the LTCC of silica filler with a low dielectric constant and that of calcium zirconate filler with a high dielectric constant, the amount of shrinkage was examined through a thermomechanical analysis, and the predicted appropriate fraction of each filler was applied to green sheets by tape casting. The green sheets of different fillers were alternatingly laminated to the thickness of 500 ㎛. As a result of examining the junction, it was observed through SEM that a complete bonding was achieved by constrained sintering in the structure of 'calcium zirconate 50 vol%-silica 30 vol%-calcium zirconate 50 vol%'.

The Sensitivity of the Parameters of Microcontroller Device with Coupling Caused by UWB-HPEM (Ultra Wideband-High Power Electromagnetics) (광대역 고출력 전자기 펄스에 의한 마이크로컨트롤러 소자의 매개변수들의 민감성 분석)

  • Hwang, Sun-Mook;Hong, Joo-Il;Huh, Chang-Su
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.2
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    • pp.369-373
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    • 2010
  • Modem electronic circuits are of importance for the function of communication, traffic systems and security systems. An intentional threat to these systems could be of big casualties and economic disasters. This paper has shown damage effect of microcontroller device with coupling caused by UWB-HPEM(Ultra Wideband-High Power Electromagnetics). The UWB measurements were done at an Anechoic Chamber using a RADAN UWB voltage source, which can generate a transient impulse of about 180 kV. The susceptibility level for microcontroller has been assessed by effect of various operation line lengths. The results of susceptibility analysis has showed that the effect of the reset line length on the MT(Ma1function Threshold) is larger than the effect of the different line length(Data, Power, Clock). With the knowledge of these parameters electronic system can be designed exactly suitable concerning the system requirements. Based on the results, susceptibility of microcontroller can be applied to protection plan to elucidate the effects of microwaves on electronic equipment.

Magnetic Saturation Effect of the Iron Core in Current Transformers Under Lightning Flow

  • Kim, Young Sun
    • Transactions on Electrical and Electronic Materials
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    • v.18 no.2
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    • pp.97-102
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    • 2017
  • A current transformer (CT) is a type of sensor that consists of a combination of electric and magnetic circuits, and it measures large ac currents. When a large amount of current flows into the primary winding, the alternating magnetic flux in the iron core induces an electromotive force in the secondary winding. The characteristics of a CT are determined by the iron core design because the iron core is saturated above a certain magnetic flux density. In particular, when a large current, such as a current surge, is input into a CT, the iron core becomes saturated and the induced electromotive force in the secondary winding fluctuates severely. Under these conditions, the CT no longer functions as a sensor. In this study, the characteristics of the secondary winding were investigated using the time-difference finite element method when a current surge was provided as an input. The CT was modeled as a two-dimensional analysis object using constraints, and the saturation characteristics of the iron core were evaluated using the Newton-Rhapson method. The results of the calculation were compared with the experimental data. The results of this study will prove useful in the designs of the iron core and the windings of CTs.

New Approach for Transient Radiation SPICE Model of CMOS Circuit

  • Jeong, Sang-Hun;Lee, Nam-Ho;Lee, Jong-Yeol;Cho, Seong-Ik
    • Journal of Electrical Engineering and Technology
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    • v.8 no.5
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    • pp.1182-1187
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    • 2013
  • Transient radiation is emitted during a nuclear explosion and causes fatal errors as upset and latch-up in CMOS circuits. This paper proposes the transient radiation SPICE models of NMOS, PMOS, and INVERTER based on the transient radiation analysis using TCAD (Technology Computer Aided Design). To make the SPICE model of a CMOS circuit, the photocurrent in the PN junction of NMOS and PMOS was replaced as current source, and a latch-up phenomenon in the inverter was applied using a parasitic thyristor. As an example, the proposed transient radiation SPICE model was applied to a CMOS NAND circuit. The CMOS NAND circuit was simulated by SPICE and TCAD using the 0.18um CMOS process model parameter. The simulated results show that the SPICE results were similar to the TCAD simulation and the test results of commercial CMOS NAND IC. The simulation time was reduced by 120 times compared to the TCAD simulation.

A Study on 3-D Analytical Model of Ion Implanted Profile (이온 주입된 프로파일의 3-D의 해석적인 모델에 관한 연구)

  • Jung, Won-Chae;Kim, Hyung-Min
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.25 no.1
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    • pp.6-14
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    • 2012
  • For integrated complementary metal oxide semiconductor (CMOS) circuits, the lateral spread for two-dimensional (2-D) impurity distributions are very important for the analyzing the devices. The measured two-dimensional SEM data obtained using the chemical etching-method matched very well with the results of the Gauss model for boron implanted samples. But the profiles in boron implanted silicon were deviated from the Gauss model. The profiles in boron implanted silicon were shown a little bit steep profile in the deep region due to backscattering effect on the near surface from the bombardments of light boron ions. From the simulated 3-D data obtained using an analytical model, the 1-D and 2-D data were compared with the experimental data and could be verified the justification from the experimental data. The data of 3-D model were also shown good agreements with the experimental and the simulated data. It can be used in the 3-D chip design and the analysis of microelectro-mecanical system (MEMS) and special devices.

A Study on implementation of Simplify Chua's Circuit without L component (L성분이 없는 간략화 Chua 회로 구현에 관한 연구)

  • Shon, Youngwoo;Bae, Youngchul
    • The Journal of the Korea institute of electronic communication sciences
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    • v.5 no.1
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    • pp.17-22
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    • 2010
  • Generally, there are Chua's Circuit, Lorenz Circuit and Duffing circuit in the chaos circuit. Among these chaos circuits, Chua's circuit is well known to make the electronic parts easily. Chua's circuit is the constitute of the linearelements. These are constitute of Resistor component(R), inductor component(L), capacitor(C), and nonlinear element which is constitute of nonlinear resistor. However, L element have a difficult problem to implement real hardware by using commercial parts. Due to this, it has a saturation characteristic. In this paper, we analyzed the simplified Chua's circuit which is replace L to C by PSPICE program. Because L element has a difficult problem to make a real hardware, L has a saturation characteristic and we also confirm this analysis as the result.

Realization of 1D-2DEG Composite Nanowire FET by Selective Area Molecular Beam Epitaxy (선택적 분자선 에픽택시 방법에 의한 1D-2DEG 혼성 나노선 FET의 구현)

  • Kim, Yun-Joo;Kim, Dong-Ho;Kim, Eun-Hong;Seo, Yoo-Jung;Roh, Cheong-Hyun;Hahn, Cheol-Koo;Ogura, Mutsuo;Kim, Tae-Geun
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.19 no.11
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    • pp.1005-1009
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    • 2006
  • High quality three-dimensional (3D) heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate to improve the efficiency of tarrier transport. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources (As2, As4) were varied to calibrate the selective area growth conditions and the 3D GaAs-AlGaAs heterostructures were fabricated into the ridge type and the V-groove type. Scanning micro-photoluminescence $({\mu}-PL)$ measurements and the following analysis revealed that the gradually (adiabatically) coupled 1D-2DEG (electron gas) field effect transistor (FET) system was successfully realized. These 3D-heterostructures are expected to be useful for the realization of high-performance mesoscopic electronic devices and circuits since it makes it possible to form direct ohmic contact onto the (quasi) 1D electron channel.

Realization of 1D-2DEG Composite Nanowire FET by Selective Area Molecular Beam Epitaxy (선택적 분자선 에피택시 방법에 의한 1D-2DEG 혼성 나노선 FET의 구현)

  • Kim, Yun-Joo;Kim, Eun-Hong;Seo, Yoo-Jung;Kim, Dong-Ho;Hahn, Cheol-Koo;Ogura, Mutsuo;Kim, Tae-Geun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.06a
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    • pp.167-168
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    • 2006
  • High quality 3D-heterostructures were constructed by selective area (SA) molecular beam epitaxy (MBE) using a specially patterned GaAs (001) substrate. MBE growth parameters such as substrate temperature, V/III ratio, growth ratio, group V sources ($As_2$, $As_4$) were varied to calibrate the selective area growth conditions. Scanning micro-photoluminescence ($\mu$-PL) measurements and following analysis revealed that the gradually (adiabatically) coupled 2DEG-1D-1DEG field effect transistor (FET) system was realized. This 3D-heterostructure is very promising for the realization of the meso-scopic electronic devices and circuits since it makes it possible to form direct ohmic contact to the (quasi) 1DEG.

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Characteristic Investigation of External Parameters for Fault Diagnosis Reference Model Input of DC Electrolytic Capacitor (DC 전해 커패시터의 고장진단 기준모델 입력을 위한 외부변수의 특성 고찰)

  • Park, Jong-Chan;Shon, Jin-Geun
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.61 no.4
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    • pp.186-191
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    • 2012
  • DC Bus Electrolytic capacitors have been widely used in power conversion system because they can achieve high capacitance and voltage ratings with volumetric efficiency and low cost. This type of capacitors have been traditionally used for filtering, voltage smoothing, by-pass and other many applications in power conversion circuits requiring a cost effective and volumetric efficiency components. Unfortunately, electrolytic capacitors are some of the weakest components in power electronic converter. Many papers have proposed different methods or algorithms to determinate the ESR and/or capacitance C for fault diagnosis of the electrolytic capacitor. However, both ESR and C vary with frequency and temperature. Accurate knowledge of both values at the capacitors operating conditions is essential to achieve the best reference data of fault judgement. According to parameter analysis, the capacitance increases with temperature and the ESR decreases. Higher frequencies make the ESR and C to decrease. Analysis results show that the proposed electrolytic capacitor parameter estimation technique can be applied to reference signal of capacitor diagnosis systems successfully.

A Study on DOE Method to Optimize the Process Parameters for Cu CMP (구리 CMP 공정변수 최적화를 위한 실험계획법(DOE) 연구)

  • Choi, Min-Ho;Kim, Nam-Hoon;Kim, Sang-Yong;Chang, Eui-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.1
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    • pp.24-29
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    • 2005
  • Chemical mechanical polishing (CMP) has been widely accepted for the global planarization of multi-layer structures in semiconductor manufacturing. Copper has been the candidate metallization material for ultra-large scale integrated circuits (ULSIs), owing to its excellent electro-migration resistance and low electrical resistance. However, it still has various problems in copper CMP process. Thus, it is important to understand the effect of the process variables such as turntable speed, head speed, down force and back pressure are very important parameters that must be carefully formulated in order to achieve desired the removal rates and non-uniformity. Using a design of experiment (DOE) approach, this study was performed investigating the main effect of the variables and the interaction between the various parameters during CMP. A better understanding of the interaction behavior between the various parameters and the effect on removal rate, non-uniformity and ETC (edge to center) is achieved by using the statistical analysis techniques. In the experimental tests, the optimum parameters which were derived from the statistical analysis could be found for higher removal rate and lower non-uniformity through the above DOE results.