• Title/Summary/Keyword: Analog-to-digital converter

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Analog-to-Digital Conveter Using Synchronized Clock with Digital Conversion Signal (디지털 변환신호와 동기화된 클록을 사용하는 아날로그-디지털 변환기)

  • Choi, Jin-Ho;Jang, Yun-Seok
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2017.10a
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    • pp.522-523
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    • 2017
  • Analog-to-Digital converter is designed using a current conveyor circuit and a time-to-digital converter. The analog voltage is sampled using the current conveyor circuit and then the voltage is converted to time information by the discharge of the sampling voltage. The time information is converted to digital value by the counter-type time-to-digital converter. In order to reduce the converted error the clock is synchronized with the time information pulse.

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Expandable Flash-Type CMOS Analog-to-Digital Converter for Sensor Signal Processing

  • Oh, Chang-Woo;Choi, Byoung-Soo;Kim, JinTae;Seo, Sang-Ho;Shin, Jang-Kyoo;Choi, Pyung
    • Journal of Sensor Science and Technology
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    • v.26 no.3
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    • pp.155-159
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    • 2017
  • The analog-to-digital converter (ADC) is an important component in various fields of sensor signal processing. This paper presents an expandable flash analog-to-digital converter (E-flash ADC) for sensor signal processing using a comparator, a subtractor, and a multiplexer (MUX). The E-flash ADC was simulated and designed in $0.35-{\mu}m$ standard complementary metal-oxide semiconductor (CMOS) technology. For operating the E-flash ADC, input voltage is supplied to the inputs of the comparator and subtractor. When the input voltage is lower than the reference voltage, it is outputted through the MUX in its original form. When it is higher than the reference voltage, the reference voltage is subtracted from the input value and the resulting voltage is outputted through the MUX. Operation of the MUX is determined by the output of the comparator. Further, the output of the comparator is a digital code. The E-flash ADC can be expanded easily.

The Design of Analog-to-Digital Converter using 12-bit Pipeline BiCMOS (12-bit 파이프라인 BiCMOS를 사용한 A/D 변환기의 설계)

  • 김현호;이천희
    • Journal of the Korea Society for Simulation
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    • v.11 no.2
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    • pp.17-29
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    • 2002
  • There is an increasing interest in high-performance A/D(Analog-to-Digital) converters for use in integrated analog and digital mixed processing systems. Pipeline A/D converter architectures coupled with BiCMOS process technology have the potential for realizing monolithic high-speed and high-accuracy A/D converters. In this paper, the design of 12bit pipeline BiCMOS A/D converter presented. A BiCMOS operational amplifier and comparator suitable for use in the pipeline A/D converter. Test/simulation results of the circuit blocks and the converter system are presented. The main features is low distortion track-and-hold with 0-300MHz input bandwidth, and a proprietary 12bit multi-stage quantizer. Measured value is DNL=${\pm}$0.30LSB, INL=${\pm}$0.52LSB, SNR=66dBFS and SFDR=74dBc at Fin=24.5MHz. Also Fabricated on 0.8um BiCMOS process.

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A 10-bit 10-MS/s 0.18-㎛ CMOS Asynchronous SAR ADC with split-capacitor based differential DAC (분할-커패시터 기반의 차동 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 0.18-㎛ CMOS 비동기 축차근사형 아날로그-디지털 변환기)

  • Jeong, Yeon-Ho;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.2
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    • pp.414-422
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    • 2013
  • This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

Comparison of TDC Circuit Design Method to Constant Delay Time

  • Choi, Jin-Ho
    • Journal of information and communication convergence engineering
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    • v.8 no.4
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    • pp.461-465
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    • 2010
  • This paper describes the design method of Time-to-Digital Converter(TDC) to obtain the constant delay time and good reliability. The reliability property is described with delay elements. In TDC the time signal is converted to digital value which is based on delay elements for the time interpolation. To obtain the constant delay time, the first and the last delay elements have different structure compared to the middle delay elements. In the first and the last delay elements, the driving ability could be controlled for the different delay time. The delay element can be designed by analog and digital devices. The delay time of the element using analog devices is not sensitive to process parameters than that of the element using digital devices. And the TDC circuit by the elements using analog devices shows better reliability than that by the elements using digital devices also.

Design of 3V a Low-Power CMOS Analog-to-Digital Converter (3V 저전력 CMOS 아날로그-디지털 변환기 설계)

  • 조성익;최경진;신홍규
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.11
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    • pp.10-17
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    • 1999
  • In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

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Implementation of CDMA Digital Transceiver using the FPGA (FPGA를 이용한 CDMA 디지털 트랜시버의 구현)

  • 이창희;이영훈
    • Journal of the Korea Society of Computer and Information
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    • v.7 no.4
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    • pp.115-120
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    • 2002
  • This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

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A Phase-Locked Loop with Embedded Analog-to-Digital Converter for Digital Control

  • Cha, Soo-Ho;Jeong, Chun-Seok;Yoo, Chang-Sik
    • ETRI Journal
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    • v.29 no.4
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    • pp.463-469
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    • 2007
  • A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

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The Remote Control of Flyback Converter using TMS320F2812 (TMS320F2812를 이용한 Flyback 컨버터의 원격제어)

  • Sim, Sang-Bo;Kim, Youn-Seo;Yang, Oh
    • Proceedings of the KIEE Conference
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    • 2004.11c
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    • pp.690-692
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    • 2004
  • Differently from an existing analog control, because the digital control includes microprocessor basically, the digital control is enable to monitor internal parameters of DC-DC converter and to control output voltage remotely by communicating with a Windows based PC and also to monitor whether exact voltage is output or not. These things are impossible in an analog control. In this paper, a simple flyback converter is taken as a control target and is controlled by a microcontroller(TMS320F2812). This converter can make variable outputs 1.8V to 5V from 30V input voltage remotely in PC. Finally the response characteristics of a step reference voltage and in a steady state are experimented to verify the feasibility and the usefulness of this digital controlled converter.

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