• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.255-258
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• 1999

This paper describes a 40-Msample/s 10-bit CMOS folding and interpolating analog-to-digital converter (ADC). A new 2-step architecture is proposed. The proposed architecture is composed of a coarse ADC bloch for the 6bits of MSBs and a fine ADC block for the remaining 4bits. The amplified folding analog signals in the coarse ADC are selectively chosen for the fine ADC. In the fine ADC, the bubble errors of the comparators are corrected by using the BGM(binary-gray-mixed) code[1] and extra two comparators are used to correct underflow and overflow errors. The proposed ADC was simulated using CMOS 0.25${\mu}{\textrm}{m}$ parameters and occupies 1.0mm$\times$1.0mm. The power consumption is 48㎽ at 40MS/s with 2.5-V power supply. The INL is under $\pm$2.0LSB and the DNL. is under $\pm$1.0LSB by Matlab simulations.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(2)
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• pp.565-568
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• 2003

The conventional analog-based firing circuit can be implemented by comparing a linearly decreasing periodic sawtooth waveform synchronized to the ac line, with a voltage corresponding to the desired converter delay angle. This circuit requires a large number of components (resistance and capacitor) and careful adjustment of the synchronization circuity In this paper a novel firing circuit is proposed for thyristor switch is elements. The proposed circuit is implemented on the basis of the analog cosine method using FPGA and microprocessor.

• 한국해양공학회:학술대회논문집
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• 한국해양공학회 2001년도 춘계학술대회 논문집
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• pp.166-171
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• 2001

A digital seismic data acquisition and processing system using a PC has been developed in order to replace the analog data acquisition system of shallow marine seismic survey. An A/D converter that has 12bits of resolution and 225KHz of conversion rate was ued to acquire data, and a data acquisition software was developed as a Windows program which provides convenience of use. Raw data acquired at field has been saved to the hard-disk simultaneously. The signal to noise ratio, vertical and horizontal resolution could be improved by a digital data processing of the raw data. The digital processing of the raw data includss gain recovery, filtering, deconvolution, and muting. With the prediction deconvolution algorithm multiple reflections appearing on the shallow marine seismic section could be removed successfully.

• 센서학회지
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• 제27권1호
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• pp.31-35
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• 2018

This paper describes a low-power, SNDR (signal-to-noise and distortion ration) enhanced SAR (successive approximation register) type 12b ADC (analog-to-digital converter) with noise shaping technique. For low power consumption and small chip size of the DAC (digital-to-analog converter), the top plate sampling technique and the dummy capacitor switching technique are used to implement 12b operation with a 10b capacitor array in DAC. Noise shaping technique is applied to improve the SNDR by reducing the errors from the mismatching of DAC capacitor arrays, the errors caused by attenuation capacitor and the errors from the comparator noise. The proposed SAR ADC is designed with a $0.18{\mu}m$ CMOS process. The simulation results show that the SNDR of the SAR ADC without the noise shaping technique is 71 dB and that of the SAR ADC with the noise shaping technique is 84 dB. We can achieve the 13 dB improvement in SNDR with this noise shaping technique. The power consumption is $73.8{\mu}W$ and the FoM (figure-of-merit) is 5.2fJ/conversion-step.

• Journal of Radiation Protection and Research
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• 제12권1호
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• pp.12-25
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• 1987

SA(Successive Approximation)형 ADC(Analog to Digital Converter)를 사용하여 방사선다중채널파고 분석기를 설계 제작하였다. 선형게이트, 윈도우 및 펄스스트레처는 논리 IC와 선형 IC들을 위주로 결합하여 구성하였으며, 분석시간이 $120{\mu}sec$인 ADC 1211(12 bit)을 중심으로 한 ADC 모듈의 메모리로는 S-RAM 6264 (Address 13 bit, Data 8 bit) 2개를 병렬로 연결하여 사용하였다. 마이크로 컴퓨터 (Apple II)가 전체 시스템을 제어하고 또 계측된 결과의 데이타를 분석할 수 있도록 인터페이스와 소프트 웨어도 만들었다. 제작된 시스템의 동작시험은 표준펄스 발생기로 $0{\sim}10V$ 사이의 일정한 펄스를 만들어 시스템에 입력시켜 그 펄스들을 계측하게 하고, 계측이 끝난 후 컴퓨터가 그 결과를 받아들여 분석하게 함으로써 이루어졌다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 D
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• pp.3201-3204
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• 2000

In general, analog tester or strip chart recorder have been used to measure the corrosion potential of structures such as gas pipelines, oil pipelines, hot water pipelines, power cables etc. Recently, automatic digital data logger substitutes for these manual equipment because using these manual equipments are tedious and time consuming. However, digital data logger also has a shortcoming, that is, short measuring time because of the short lifetime of batteries. Therefore, we developed a long lifetime and low power loss battery taking advantage of galvanic series. In this paper, the results of development for power generator using two metals and DC/DC converter in order to obtain enough voltage for the operation of digital data logger. DC/DC converter operates with 0.5[V]. Its output voltage is 3.5[V] and output current is from 60[mAh] to 1,200[mAh].

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.371-374
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• 2013

본 논문에서는 빛 에너지 하베스팅을 이용한 센서 노드 회로를 제안한다. 솔라셀에서 변환된 에너지는 PMU(Power Management Unit)를 통해 관리되고, 일정한 전압을 공급하기 위해 LDO(Low Drop Out Regulator)를 사용한다. LDO를 통해 공급된 전압으로 온도센서와 SAR ADC(Successive Approximate Register Analog-to-Digital Converter)를 구동시킨다. 이 회로는 0.35um CMOS 공정으로 설계되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권1호
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• pp.43-50
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• 2007

In a high-speed flash style or a pipelining style analog-to-digital converter (A/D converter), the DC reference fluctuation caused by external noises becomes serious, as the sampling frequency is increased. To reduce the fluctuations in conventional A/D converters, capacitors have been simply used, but the layout area was large. Instead of capacitors, a low-noise and small-size DC reference circuit based on transmission gate (TG) is proposed in this paper. In order to verify the proposed technique, we designed and manufactured a 6-bit 2GSPS CMOS A/D converter. The A/D converter is designed with a 0.18um 1-poly 6-metal n-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies the chip area of 977um by 1040um. The measured result shows that SNDR is 36.25 dB and INL/DNL is within 0.5LSB, even though the DC reference fluctuation is serious.

• 대한전자공학회논문지
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• 제18권5호
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• pp.1-9
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• 1981

4-bit 전하결합 A/D 변환기에 대한 실험 결과를 제시하였다. Successive approximation algorithm 에 필요한 대개의 기능을 CCADC(charge coupled A/D converter)라는 mono-lithiic chip으로 실현하였다. CCADC는 P-channel 전하결합소자 제작기술에 의하여 만들어졌으며, Chip면적은 약 4,200 $mil^2$이었다. 동작 clock 주파수 범위는 500Hz ~ 200KHz로 나타났으며, 이 주파수 범위내에서는 약 2.4 Volt의 전신호 전압 구간을 1LSB/clok주기의 속도로 변하는 ramp 입력신호에 대하여 16가지의 binary code가 빠짐없이 관찰되었다. MSB단부터 LSB단의 순서로 정격 전하용량이 각각 3.6pC, 1.8pC, 0.9pC, 0.45pC인 4개의 연속된 potential well(M-well)간의 면적비를 (8:4:2:1)로 유지하기 위한 설계기술에 대하여 토론하였다. 끝으로, 제작된 A/D변환기에 있어서 과도한 conversion nonlinearity의 원인이 되는 dumpslot 효과에 대하여 설명하였으며, dump slot으로 인한 오동작을 막기 위한 방법으로서 slot zero 삽입방식을 제안하고 이에 대한 실험결과를 제시하였다.

• 한국전자통신학회논문지
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• 제14권6호
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• pp.1145-1152
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• 2019

본 논문에서는 디지털 회로와 저소비전력 및 고속연산의 장점을 가진 아날로그 회로를 혼용하기 위하여, 저전력 전류모드 12비트 ADC(: Analog to Digital Converter)를 제안하였다. 제안하는 12비트 ADC는 4비트 ADC의 cascade 구조를 사용하여 소비전력을 줄일 수 있었으며, 변환 current mirror 회로를 사용해 칩면적을 줄일 수 있었다. 제안된 ADC는 매그나칩/SK하이닉스 350nm 공정으로 구현하였고, Cadence MMSIM을 사용하여 post-layout simulation를 진행하였다. 전원전압 3.3V에서 동작하고, 면적은 318㎛ x 514㎛를 차지하였다. 또한 제안하는 ADC는 평균 소비전력 3.4mW의 저소비전력으로 동작하는 가능성을 나타내었다.