• Journal of Power Electronics
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• 제17권3호
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• pp.686-694
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• 2017

Due to the wide use of electronic products, digitally controlled DC-DC converters are attracting more and more attention in recent years. However, digital control strategies may introduce undesirable Limit Cycle Oscillation (LCO) due to quantization effects in the Analog-to-Digital Converter (ADC) and Digital Pulse Width Modulator (DPWM). This results in decreases in the quality of the output voltage and the efficiency of the system. Meanwhile, even if the resolution of the DPWM is finer than that of the ADC, LCO may still exist due to improper parameters of the digital compensator. In order to discover how LCO is generated, the state space averaging model is applied to derive equilibrium equations of a digital PID controlled DC-DC converter in this paper. Furthermore, the influences of the parameters of the digital PID compensator, and the resolutions of the ADC and DPWM on LCO are studied in detail. The amplitude together with the period of LCO as well as the corresponding PID parameters are obtained. Finally, MATLAB/Simulink simulations and FPGA verifications are carried out and no-LCO conditions are obtained.

• 전력전자학회논문지
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• 제9권5호
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• pp.485-490
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• 2004

본 논문에서는 나노급 서보 전동기의 초정밀 위치제어를 위한 위치정보를 얻기 위하여 정현파 엔코더에 적용하기 위한 새로운 위치 보간 알고리즘에 대하여 기술한다. 기존의 정현파 엔코더에서 사인 및 코사인 파형에서 정밀위치정보를 얻기 위하여 대용량의 메모리와 빠른 변환속도를 갖는 2개의 A/D를 이용하였다. 그러나 제안된 보간 방법을 이용할 경우에는 적은 용량의 메모리와 단지 하나의 A/D와 비교기만을 이용하여 정현파 엔코더에서 정밀위치정보를 얻을 수 있다. 초정밀 제어를 위한 제안된 알고리즘의 유용성은 실험결과로부터 알 수 있다.

• 한국의학물리학회:학술대회논문집
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• 한국의학물리학회 2002년도 Proceedings
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• pp.468-470
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• 2002

We have designed X-ray detection system and multi-channel data acquisition system for Spiral CT application. X-ray detection system consists of scintillator and photodiode. Scintillator converts X-ray into visible light. Photodiode converts visible light into electrical signal. The multi-channel data acquisition system consists of analog, digital, master and backplane board. Analog board detects electrical signal and amplifies signal by 140dB. Digital board consists of MUX(Multiplex) which routes multi-channel analog signal to preamplifier, and ADC(Analog to Digital Converter) which converts analog signal into digital signal. Master board supplies the synchronized clock and transmits the digital data to image reconstructor. Backplane provides electrical power, analog output and clock signal. The system converts the projected X-ray signal over the detector array with large gain, samples the data in each channel sequentially, and the sampled data are transmitted to host computer in a given time frame. To meet the timing limitation, this system is very flexible since it is implemented by FPGA(Field Programmable Gate Array). This system must have a high-speed operation with low noise and high SNR(signal to noise ratio), wide dynamic range to get a high resolution image.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.129-140
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• 2017

In this paper, a $4{\times}32$-channel neural recording system capable of acquiring neural signals is introduced. Four 32-channel neural recording ICs, complex programmable logic devices (CPLDs), a micro controller unit (MCU) with USB interface, and a PC are used. Each neural recording IC, implemented in $0.18{\mu}m$ CMOS technology, includes 32 channels of analog front-ends (AFEs), a 32-to-1 analog multiplexer, and an analog-to-digital converter (ADC). The mid-band gain of the AFE is adjustable in four steps, and have a tunable bandwidth. The AFE has a mid-band gain of 54.5 dB to 65.7 dB and a bandwidth of 35.3 Hz to 5.8 kHz. The high-pass cutoff frequency of the AFE varies from 18.6 Hz to 154.7 Hz. The input-referred noise (IRN) of the AFE is $10.2{\mu}V_{rms}$. A high-resolution, low-power ADC with a high conversion speed achieves a signal-to-noise and distortion ratio (SNDR) of 50.63 dB and a spurious-free dynamic range (SFDR) of 63.88 dB, at a sampling-rate of 2.5 MS/s. The effectiveness of our neural recording system is validated in in-vivo recording of the primary somatosensory cortex of a rat.

• 전자공학회논문지C
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• 제35C권4호
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• pp.50-59
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• 1998

This paper describes a 3.3V 8bit CMOS digital to analog converter (DAC) with two state current cell metrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allow the designed DAC to reduce hot only a complexity of decoding logics, but also a number of wider swing cascode curent mirros. The designed DAC with an active chip area of 0.8 mm$_{2}$ is fabricated by a 0.8 .mu.m CMOS n-well standard digital process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are6ns, 15ns, and a less than .+-.0.8/.+-.0.75 LB, respectively. The designed DAC is fully operational for the power supply down to 2.0V, such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3V is measured to be 34.5mW.

• 한국전자파학회논문지
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• 제12권5호
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• pp.817-826
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• 2001

본 논문에서는 TI(Texas instrument)사의 범용 DSP 프로세서인 TMS320C31을 이용하여 통신 시스템에서 많이 사용되는 QPSK 방식의 모뎀을 구현하였다. 지금까지 거의 모든 시스템의 신호 변환 과정은 하드웨어로 구성되어 있지만, 본 논문에서 구현된 시스템은 QPSK 신호의 변조과정에서 IF단의 DAC를 통과하기 이전까지의 과정과 복조과정에서 IF단의 ADC를 통과한 이후의 과정을 프로그램으로 구성하고, 신호의 입.출력부와 처리부분을 하드웨어로 구성하였다. DSP 프로세서를 이용한 모뎀 출력 결과를 PC 상에서 시뮬레이션 결과와 비교하여 제작한 모뎀이 정상적으로 동작됨을 확인하였다.

• 한국전자통신학회논문지
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• 제7권5호
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• pp.1061-1066
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• 2012

디지털 메모리는 신뢰성, 속도 그리고 상대적인 단순한 제어회로로 인해 지금까지 저장장치로서 널리 사용되어 왔다. 그러나 디지털 메모리 저장능력은 공정의 선폭감소의 한계로 인해 결국 한계에 다다르게 될 것이다. 이러한 저장 능력을 획기적으로 증가시키는 방안의 하나로서 메모리의 셀에 저장하는 데이터의 형태를 디지털에서 아날로그로 변화시키는 것이다. 한 개의 셀과 프로그래밍을 위한 주변회로로 구성된 아날로그 메모리가 0.16um 표준 CMOS 공정에서 제작되었다. 제작된 아날로그 메모리는 저밀도 불활성 메모리, SRAM과 DRAM에서 리던던시 회로 제어, ID나 보안코드 레지스터, 영상이나 음성 저장장치 등에 응용될 것이다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.562-564
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• 2002

Noise reduction and a simplification of a precision measurement system has been performed by changing analog output mode of a load cell into digital output mode. Usually, analog output signal of a few $\mu V$ from a load cell are amplified by amp and acquired by A/D converter. If the distance from a load cell to a DAS(Data Acquisition System) increases, more noise signals are mixed. So, a microprocessor has been integrated into a load cell so that the amplification and A/D conversion of output signals could be done in close proximity to the lode cell for the reduction in mixing of noise. Obtained data from the load cell like this manner are transferred to a computer with digital values(of TTL level). To simplify the configuration of a multi-channel DAS, RS-485 communication system has used for data transfer.

• Journal of Power Electronics
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• 제14권4호
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• pp.796-805
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• 2014

A digital controller with a low-power approach for point-of-load synchronous buck converters is discussed and compared with its analog counterpart to confirm its feasibility for system integration. The tri-mode digital controller IC in $0.35{\mu}m$ CMOS process is presented to demonstrate solutions that include a PID, quarter PID, and robust RST compensators. These compensators address the steady-state, stand-by, and transient modes according to the system operating point. An idle-tone free condition for ${\Sigma}-{\Delta}$ DPWM reduces the inherent tone noise under DC-excitation. Compared with that of the traditional approach, this condition generates a quasi-pure modulation signal. Experimental results verify the closed-loop performances and confirm the power-saving mechanism of the proposed controller.

• ETRI Journal
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• 제46권2호
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• pp.238-249
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• 2024

Equivalent-time sampling can improve measurement or sensing systems because it enables a broader frequency band and higher delay resolution for periodic signals with lower sampling rates than a Nyquist receiver. Meanwhile, a digital down-conversion (DDC) technique can be implemented using a straightforward radio frequency (RF) circuit. It avoids timing skew and in-phase/quadrature gain imbalance instead of requiring a high-speed analog-to-digital converter to sample an intermediate frequency (IF) signal. Therefore, when equivalent-time sampling and DDC techniques are combined, a significant synergy can be achieved. This study provides a parameter design methodology for optimal equivalent-time sampling using DDC.