• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.49 no.11
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• pp.933-940
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• 2021

The space-borne SAR(Synthetic Aperture Radar) system radiates the microwave signal and receives the backscattered signal. The received signal is converted to digital at the Digital Receiver, which is implemented at the end of the SAR sensor receiving chain. The converted signal is formated after signal processing such as filtering and data compression. Two quantization are conducted in the Digital Receiver. One quantization is an analog to digital conversion at ADC(Analog-Digital Converter). Another quantization is the BAQ(Block Adaptive Quantization) for data compression. The quantization process is a conversion from a continuous or higher bit precision to a discrete or lower bit precision. As a result, a quantization noise is inevitably occurred. In this paper, the impact of two quantization processes are analyzed in a view of SNR degradation.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.164-167
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• 2000

This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65 $\mu\textrm{m}$ CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.281-283
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• 2016

Recently, many industrial instruments face the problem of protocol compatibility with the external monitoring and control system. This paper is prepared in the main control board to support the industrial communication protocol conversion, control, and monitoring. The industrial communication gateway module is also designed to ensure that the protocol conversion of CAN bus and Ethernet. The main board processor is used the Atmega2560, and placed 4ea RS485 serial slots for sub-board. One of them is used for communication CAN bus and Ethernet. It provides analog and digital I / O through each of the slots is used for control and monitoring.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.84-86
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• 2005

The digital systems such as PLC or DCS have been applied to non-safety systems of nuclear power plants because of many difficulties in using analog systems. Nowadays, digital systems have been applied to safety systems of the plants such as reactor protection system. One of the main advantages of digital systems is applicability of automatic testing methods to the systems. The protection system requires high-reliability and high-availability because it shall minimize the propagation of abnormal or accident conditions of nuclear power plants. The calculation of reliability and availability of systems depends on the maintenance period of the system. In general, the maintenance period of the protection system is one-month in case of the manual test. However, the cycle of test can be shortened in several hours by using automatic periodic testing. The reliability and availability of the system is better when test period is shortened because the reliability and availability is inverse proportion to the test period. In this research, we developed the automatic periodic testing method for KNICS Reactor Protection System, which can test the system automatically without an operator or a tester. The automatic testing contained all functions of reaction protection systems from analog-to-digital conversion function of the bistable Processor to the coincident trip function of the coincident processor. By applying the automatic periodic testing to reaction system, the maintenance cost can be cut down and the reliability can be increased.

• ETRI Journal
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• v.36 no.6
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• pp.894-904
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• 2014

Blind mismatch correction of time-interleaved analog-to-digital converters (TI-ADC) is a challenging task. We present a practical blind calibration technique for low-computation, low-complexity, and high-resolution applications. Its key features are: dramatically reduced computation; simple hardware; guaranteed parameter convergence with an arbitrary number of TI-ADC channels and most real-life input signals, with no bandwidth limitation; multiple Nyquist zone operation; and mixed-domain error correction. The proposed technique is experimentally verified by an M = 4 400 MSPS TI-ADC system. In a single-tone test, the proposed practical blind calibration technique suppressed mismatch spurs by 70 dB to 90 dB below the signal tone across the first two Nyquist zones (10 MHz to 390 MHz). A wideband signal test also confirms the proposed technique.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.6
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• pp.726-731
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• 2004

This paper proposes a pulse-width-modulation (PWM) controller design technique using intelligent digital redesign. Intelligent digital redesign is to convert a well-designed analog fuzzy-model-based controller into an equivalent pulse-amplitude-modulation (PAM) digital controller maintaining the original analog control system in the sense of state-matching. In similar line of conversion concept, the redesigned PAM intelligent digital controller is converted into a PWM controller using the equivalent area principle. To convincingly visualize the proposed technique, an computer simulation example-attitude control of nonlinear artificial satellite system is included.

• Korean Journal of Remote Sensing
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• v.30 no.2
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• pp.251-258
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• 2014

We upgraded to utilize a novel method for combining the analog to digital converter and photon-counting measurements for backscatter photon signal of lidar. We have and improve the standard combining method for determination of those conversion factors between analog to digital converter data and photon-counting data measurement which is conducted dead time correction. The combining method and dead time correction method presented here has been successfully applied to experimental data obtained in Gwangju, Korea.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1701-1705
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• 2004

This paper presents a design and analysis of electromechanical sigma-delta modulator for MEMS gyroscope, which enables us to control the proof mass and to obtain an exact digital output without additional A/D conversion. The system structure and the circuit realization of the sigma-delta modulation are simpler than those of the analog sensing and feedback circuit. Based on the electrical sigma-delta modulator theory, a compensator is designed to improve the closed loop resolution of the sensor. With the designed compensator, we could obtain enhanced closed-loop performances of the gyroscope such as larger bandwidth, lower noise, and digital output comparing with the results of analog open-loop system.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.569-572
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• 2004

This paper presents a 12-Bit 250MHz CMOS current-mode Digital to Analog Converter(DAC) with current scalers and dividers. It consist of 4 MSB current scaler, 4 MLSB current divider, and 4 LSB current divider. The simulation results show a conversion rate of 250MHz, DNL/INL of ${\pm}5LSB/{\pm}7LSB$, die area of $0.55mm^2$ and Power dissipation of 27mW at 3.3V