• Proceedings of the IEEK Conference
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• summer
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• pp.199-203
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• 2004

In this paper, we only describe the digital block of two-channel 18-bit analog-to-digital (A/D) converter employing sigma-delta method and xl28 decimation. The device contains two fourth comb filters with 1-bit input from sigma­delta modulator. each followed by a digital half band FIR(Finite Impulse Response) filters. The external analog sigma-delta modulators are sampled at 6.144MHz and the digital words are output at 48kHz. The fourth-order comb filter has designed 3 types of ways for optimal power consumption and signal-to-noise ratio. The following 3 digital filters are designed with 12tap, 22tap and 116tap to meet the specification. These filters eliminate images of the base band audio signal that exist at multiples of the input sample rate. We also designed these filters with 8bit and 16bit filter coefficient to analysis signal-to-noise ratio and hardware complexity. It also included digital output interface block for I2S serial data protocol, test circuit and internal input vector generator. It is fabricated with 0.35um HYNIX standard CMOS cell library with 3.3V supply voltage and the chip size is 2000um by 2000um. The function and the performance have been verified using Verilog XL logic simulator and Matlab tool.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.68-71
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• 1986

A new circuit configuration for charge-balancing successive approximation Analog-to-Digital converters is described. This consists of a improved successive approximation register(SAR) and a weighted capacitor Digital-to-Analog converter (WCDAC). Due to the inherent conversion property of the WCDAC, the A/D converter using the WCDAC can be simply implemented by successive approximation conversion method, and 4bit monotonicity conversion with differential nonlinearity less 1/2LSB is completed in 80 US.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.414-422
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• 2013

This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

• ETRI Journal
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• v.29 no.6
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• pp.835-837
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• 2007

A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 ${\mu}m$ CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.

• Journal of Korea Society of Digital Industry and Information Management
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• v.13 no.3
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• pp.35-42
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• 2017

This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.11-21
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• 1999

This paper has been proposed a structure composed of FIRs and IIR filters as digital interpolation filter to integrate the off-chip analog low-pass filter of audio DAC. The passband ripple (>$0.41{\times}fs$), passband attenuation(>at$0.41{\times}fs$) and stopband attenuation(<$0.59{\times}fs$) of the ${\Delta}{\Sigma}$ modulator output using the proposed digital interpolation filter had ${\pm}0.001[dB]$, -0.0025[dB] and -75[dB], respectively. Also the inband group delay was 30.07/fs[s] and the error of group delay was 0.1672%. Also, the attenuation of stopband has been increased -20[dB] approximately at 65[kHz], out-of-band. Therefore the RC products of analog low-pass filter on chip have been decreased compared with the conventional digital interpolation filter structure.

• Journal of IKEEE
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• v.2 no.2 s.3
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• pp.309-315
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• 1998

This paper describes an 8b 52 MHz CMOS subranging analog-to-digital converter (ADC) for Integrated Services Digital Network (ISDN) applications. The proposed ADC based on the improved time-interleaved architecture removes the holding time which is typically observed in the conventional double-channel subranging ADCs to increase throughput rate. Moreover, the ADC employs the interpolation technique in the back-end subranging ADCs far residue signal processing to minimize die area and power consumption. The fabricated and measured prototype ADC in a 0.8 um n-well double-poly double-metal CMOS process typically shows a 52 MHz sampling rate at a 5 V supply voltage with 230 mW, and a 40 MHz sampling rate at a 3 V power supply with 60 mW power consumption.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 1996.06c
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• pp.569-581
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• 1996

A microcomputer -based data acquistion system was designed and developed at Michigan State University , USA to conduct field data studies. The system designed for the research carried out used an Apple IIe microcomputer for collecting data on-board the tractor. An AII3 Analog to Digital (A/D_ convertor was chosen to interface each analog signal to the microcomputer. A commercially available Dj TPM II was employed to display information such as an engine speed, ground speed, percent drive wheel slip , distance travelled and area covered per hour. The frequency output from the radar unit was channeled through a frequency to voltage (F/V) convertor , so that AII3 Analog to Digital (A/D) convertor could read it. The fuel consumption was measured using on EMCO pdp-1 fuel flow meter attached to the engine fuel line. The draft of the tillage and other drag equipment was determined using strain gages attached to the drawbar of the tractor. The system was developed to collect the draft and fuel requirements for various farm equipment different kind of soils.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.562-564
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• 2002

Noise reduction and a simplification of a precision measurement system has been performed by changing analog output mode of a load cell into digital output mode. Usually, analog output signal of a few $\mu V$ from a load cell are amplified by amp and acquired by A/D converter. If the distance from a load cell to a DAS(Data Acquisition System) increases, more noise signals are mixed. So, a microprocessor has been integrated into a load cell so that the amplification and A/D conversion of output signals could be done in close proximity to the lode cell for the reduction in mixing of noise. Obtained data from the load cell like this manner are transferred to a computer with digital values(of TTL level). To simplify the configuration of a multi-channel DAS, RS-485 communication system has used for data transfer.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.89-92
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• 2001

In this paper, as a study of programmable software radio digital communication, we implemented ASK(Amplitude Shift Keying), FSK(Frequency Shift Keying), and PSK(Phase Shift Keying) modulation using programmable software(algorithm) of DSP(Digital Signal Processor). Moreover, it is possible to select one of those three modulation methods by realizing on single DSP. We adopted Motorola DSP56002 and Crystal CS4215(A/D and D/A converter) for our purpose. The DSP56002 is 24-bit and operates 20 MIPS at 40 MHz, and the CS4215 is 16-bit and supports the maximum 50 kHz sampling frequency.