• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1887-1894
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• 2010

This paper proposes a new switched-capacitor sigma-delta modulator for automotive radars. Developed modulator is used to perform high-resolution analog-to-digital conversion (ADC) of high frequency band signal in a radar system. It has supply voltage of 2.7V, and has body-effect compensated switch configuration with low voltage and low distortion. The modulator has been implemented in a $0.25{\mu}m$ double-poly and triple-metal standard CMOS process, and it has die area of $1.9{\times}1.5mm^{2}$. It showed better total harmonic distortion of 20dB than the conventional bootstrapped circuit at the supply voltage of 2.7V.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.9
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• pp.833-839
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• 2011

This paper has suggested a technique for measuring VSWR at 1.8 GHz band for various modulated signals. By using directional coupler the power of incident and reflected wave is measured, and in order to minimize the size and cost of the measuring circuit, a SPDT(Single Pole Double Throw) switch is adopted to realize the circuit with just one detector and one A/D(Analog to Digital) converter. MCU(Micro Control Unit) is used to calculate the voltage reflection coefficient and VSWR, and the measured VSWR error has improved by approximately 0.2 with applying a simple bubble sorting algorithm to reduce the measurement error, the MCU process time and load.

• Nuclear Engineering and Technology
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• v.32 no.4
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• pp.316-327
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• 2000

The Emergency Core Cooling System in current nuclear power plants typically has a considerable number of complex functions and largely cumbersome operator interfaces. Functions for initiation, switch-over between various phases of operation, interlocks, monitoring, and alarming are usually performed by relays and analog comparator logic which are difficult to maintain and test. To improve problems of an analog based ECC (Emergency Core Cooling) System, the trip computer for ECCS based on Dynamic Safety System (DSS) is implemented. The DSS is a computer based reactor protection system that has fail-safe nature and performs a dynamic self-testing. The most important feature of the DSS is the introduction of test signal that send the system into a tripped state. The test signals are interleaved with the plant signals to produce an output which switches between a tripped and health state. The dynamic operation is a key feature of the failsafe design of the system. In this work, a possible implementation of the DSS using PLC is presented for a CANDU Reactor. ECC System of the CANDU Reactor is selected as the reference system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1597-1602
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• 1999

An analog / digital mixed mode frequency multiplication and distribution ASIC for switch link or network synchronization of ATM switching system for B-ISDN has designed. This ASIC generates 234-7 MHz system clock and 77.76 MHz, 19.44 MHz user clocks using 46.94 MHz external clock. It also includes digital circuits for checking and selecting between the two external clocks. For effective ASIC design, full custom technique is used in analog PLL circuit and standard cell based technique is used in digital circuit. Resistors and capacitors are specially designed so the chip can be implemented in 0.8$\mu\textrm{m}$ digital CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Broadcasting and Media Magazine
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• v.17 no.2
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• pp.6-17
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• 2012

지상파방송사들의 ASO(Analog Switch-Off, 아날로그 방송 종료) 이후에 유휴대역으로 남게 되는 700MHz 대역(채널당 6MHz, 698MHz~806MHz 총 108MHz)은 4세대(4G : 4Generation) 방송과 이동통신 분야, 공공서비스 등에 활용될 수 있다. 700MHz 주파수 대역에 대해서 방송업계에서는 3D UHD방송 등 4G방송(3D UHD방송)을 위해서 주파수가 필요하다고 주장하고 있으며, 통신업계에서는 늘어나는 데이터 트래픽의 해소 및 4G 이동통신을 위해 통신분야에 배정해야 한다는 주장을 펴고 있다. 이러한 상황에서 지금까지 700MHz 대역의 활용에 관한 대부분의 연구는 이동통신 중심이었다. 그래서 700MHz 대역의 공익적 활용에 관한 본고는 주파수의 주인인 시청자의 시청권 보호 및 차세대방송 서비스의 활성화를 위해서 지상파방송의 차세대서비스(4G방송)를 위한 방송용주파수 정책마련의 필요성을 제시하였다.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.166-170
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• 1997

A Single phase induction motor is the predominant fractional horsepower power rated, extensively used in domestic and industrial application. For example, these motors provide the motive power to washing machines, fans, refrigerators, etc. In this paper, single phase induction motor input current was detected by a small current transformer and determined TRIAC gate signal by using op-amp analog circuit. The soft-start strategy is based on limited auxiliary current angle during starting period in the closed-loop control. The Simulation and experimental result show the motor's starting characteristics of the proposal starting system and are compared with centrifugal switch starting motor.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1363-1374
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• 2009

This paper reviews the characteristics and technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1559_1560
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• 2009

본 논문은 고출력 전자파인 HPM(High Power microwave)에 대해서 아날로그 스위치 칩이 어떠한 영향을 받는지를 규명하는데 목적이 있다. 이때 아날로그 스위치 칩은 기판위에서 동작시키면서 분석하였다. 아날로그 스위치를 on/off 시키면서 정상동작 할 때의 입력과 출력을 시간영역에서 분석한 후에 외부에서 고출력 마이크로파를 입사시켜 주었다. 칩이 고출력 마이크로파에 직접노출 되었을 때의 입력과 출력을 시간영역에서 분석하고 정상동작할 때의 입력, 출력과 비교분석하였다. 이는 고출력 전자파가 외부전자장비에 입사되어졌을 때, 외부전자장비가 영향을 받아 오작동을 한다는 것을 규명한다.

• Proceedings of the KWS Conference
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• 2000.04a
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• pp.99-102
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• 2000

Conventionally, ZVS FB DC/DC converter was controlled by monolithic IC UC3879, which includes the functions of oscillator, error amplifier and phase-shift circuit. Also, microprocessor and DSP have been widely used for the remote control and for the immediate waveform control in ZVS FB DC/DC converter. However the conventional microprocessor controller is complex and difficult to control because the controller consists of analog and digital parts. In the case of the control of FB DC/DC converter, the output is required of driving a direct signal to the switch drive circuits by the digital controller. So, this paper presents the method and realization of designing the digital-to-phase shift PWM circuit controlled by DSP (TMX320C32) in a 2,500A, 40㎾ WS FB DC/DC converter.