• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.2
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• pp.54-61
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• 1999

This paper describes the design of a 4-Mbps wireless infrared data transceiver chip. The receiver consits of the analog front-end, clock recovery and frame generator, and demodulator. The transmitter consists of the demodulator and LED driver. The versatile analog front- end consisting of multiple amplifiers makes it possible for the chip to be applied to various infrared environments by compensating DC and offset signal components. A 4PPM (pulse position modulation) scheme is used for data transfer in order to meet the IrDA standards. The chip was fabricated in a $0.8-{\mu}m$ 2-poly, 2-metal CMOS technology and dissipates 122mW for ${\pm}2.5V$ supply.

• Journal of IKEEE
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• v.15 no.4
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• pp.324-329
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• 2011

In recent years, the performance and functions of portable devices has increased. so it requires more power efficiency and energy density while using the battery for a long time. therefore Battery pack which are made up from several battery cells in series in order to achieve higher operating voltage is being used. when using a Li-ion battery, we need a protection circuit to protect from overcharge, over discharge, high temperature and over current. Also, when using battery pack, we need to Cell voltage balancing circuit that each cell in tune with the balancing. In this paper, the proposed IC is applicable by mobile devices as well as E-bike, hybrid vehicles, electric vehicles, and is expected to contribute to the development of domestic PMIC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.130-136
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• 2008

This paper describes a low-power high-performance analog front-end block for $UHF(860{\sim}960MHz)$ band RFID tag chips. It satisfies ISO/IEC 18000-6 type C(EPCgolbal class1. generation2.) and includes a memory block for test. For reducing power consumption, it operates with a internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator has an error rate as low as 0.014%. It is designed using a 0.18um CMOS technology. The simulation results show that the designed circuit can operate properly with an input as low as $0.2V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1709-1716
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• 2007

In this paper, ADC with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB$ and $0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.261-268
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• 2014

This paper presents a electrocardiogram(ECG), electromyogram(EMG), and Photoplethysmography(PPG) signal wireless monitoring system based on Bluetooth Low Energy (BLE). ECG and EMG sensor interface analog front-end circuits are designed by using off-the-shelf parts. Texas Instruments(TI)'s CC2540DK is used for BLE-based communication. Two CC2540DK modules are used as Peripheral and Central nodes. In peripheral device, vital signals are acquired by the analog front-ends and fed to ADC for analog-to-digital conversion. The peripheral transmitts the data through the air to the central device. The central device receive the data and sends them to PC using UART. GUI is designed using Labview for displaying the acquired vital signals. The developed system can be used for future ubiquitous wireless healthcare system based on bluetooth 4.0.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.3
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• pp.69-80
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• 2015

This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1141-1144
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• 2003

For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

• ETRI Journal
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• v.34 no.2
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• pp.216-225
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• 2012

This paper presents a transceiver module for human body communications whereby a spread signal with a group of 64 Walsh codes is directly transferred through a human body at a chip rate of 32 Mcps. Frequency selective digital transmission moves the signal spectrum over 5 MHz without continuous frequency modulation and increases the immunity to induced interference by the processing gain. A simple receiver structure with no additional analog circuitry for the transmitter has been developed and has a sensitivity of 250 ${\mu}V_{pp}$. The high sensitivity of the receiver makes it possible to communicate between mobile devices using a human body as the transmission medium. It enables half-duplex communication of 2 Mbps within an operating range of up to 170 cm between the ultra-mobile PCs held between fingertips of each hand with a packet error rate of lower than $10^{-6}$. The transceiver module consumes 59 mA with a 3.3 V power supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.1-11
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• 2008

This work proposes a 15b 50MS/s CMOS pipeline ADC based on digital code-error calibration. The proposed ADC adopts a four-stage pipeline architecture to minimize power consumption and die area and employs a digital calibration technique in the front-end stage MDAC without any modification of critical analog circuits. The front-end MDAC code errors due to device mismatch are measured by un-calibrated back-end three stages and stored in memory. During normal conversion, the stored code errors are recalled for code-error calibration in the digital domain. The signal insensitive 3-D fully symmetric layout technique in three MDACs is employed to achieve a high matching accuracy and to measure the mismatch error of the front-end stage more exactly. The prototype ADC in a 0.18um CMOS process demonstrates a measured DNL and INL within 0.78LSB and 3.28LSB. The ADC, with an active die area of $4.2mm^2$, shows a maximum SNDR and SFDR of 67.2dB and 79.5dB, respectively, and a power consumption of 225mW at 2.5V and 50MS/s.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.