• Proceedings of the Korean Information Science Society Conference
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• 2010.06b
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• pp.324-327
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• 2010

최근 카메라 센서는 ISP(Image Signal Processor)를 별도로 사용하지 않고 SOC(System on Chip) 방식으로 설계를 하여 소형화를 추구하고 있지만, High Resolution의 카메라가 개발 요구되어지면서 센서 Pixel 및 스위칭 트랜지스터의 집적화가 심화되고 있다. 이러한 고집적화는 카메라 센서 내 발열 관리에 대한 관심을 높여주고 있다. 본 논문에서는 우선 SOC 센서가 ISP를 탑재한 센서이므로 프로세서 발열 관리 기법에 대해 먼저 소개를 한 후, SOC 방식 센서를 대상으로 열이 발생되는 관련 조건을 확인 검사하고, 분석한 결과를 보인다. 또한 이러한 분석 결과를 토대로 발열을 제어 할 수 있는 방법으로 DAC(Digital Analog Converter)를 사용하여 센서 내 사용되는 전류 증폭을 최소화 한 설계 방식에 대해 분석해 보았으며, 전류 증폭을 최소화한 결과 최대 PCLK(Pixel Clock)에서도 열화에 따른 Noise(Hot Pixel)를 개선시킬 수 있었다.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.11a
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• pp.1089-1092
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• 2004

This paper deals with the development of a contact-type counting device using a piezoelectric polymer film as a sensor. The piezoelectric and vibration characteristics of the film under a bending vibration were investigated theoretically and experimentally. A counting device, which includes filters, an amplifier, an analog-digital converter, and a display, was designed and fabricated. The performance of the piezoelectric polymer sensor was evaluated in the sense of the responses to contact force, contact frequency, and contact speed. The life and the temperature effect were also investigated for the piezoelectric film sensor.

• Journal of Sensor Science and Technology
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• v.30 no.5
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• pp.295-299
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• 2021

In this study, we present a complementary metal-oxide-semiconductor (CMOS) binary image sensor. It can shoot an object rotating at a high-speed by using a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector. The GBT PMOSFET-type photodetector amplifies the photocurrent generated by light. Therefore, it is more sensitive than a standard N+/P-substrate photodetector. A binary operation is installed in a GBT PMOSFET-type photodetector with high-sensitivity characteristics, and the high-speed operation is verified by the output image. The binary operations circuit comprise a comparator and memory of 1- bit. Thus, the binary CMOS image sensor does not require an additional analog-to-digital converter. The binary CMOS image sensor is manufactured using a standard CMOS process, and its high- speed operation is verified experimentally.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.293-294
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• 2014

본 논문에서는 MOS 커패시터를 이용하여 12비트 1MSps 연속 근사화 레지스터 아날로그-디지털 변환기(Successive Approximation Register Analog-to-Digital Converter, SAR ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 매그나칩/SK하이닉스 $0.18{\mu}m$ 공정을 이용하였으며, Cadence Tool을 이용하여 시뮬레이션 및 레이아웃을 하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 3.22mW였고, 유효 비트수는 11.5bit의 결과를 보였다.

• Journal of Semiconductor Engineering
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• v.1 no.3
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• pp.81-87
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• 2020

An instrumentation amplifier (IA) and an analog-to-digital converter (ADC) are essential circuit blocks for accurate and robust sensor readout systems. This paper introduces recent advances in radiation-hardening by design (RHBD) techniques applied for the sensor readout integrated circuits (IC), e.g., the three-op-amp IA and the successive-approximation register (SAR) ADC, operating against total ionizing dose (TID) and singe event effect (SEE) in harsh radiation environments. The radiation-hardened IA utilized TID monitoring and adaptive reference control to compensate for transistor parameter variations due to radiation effects. The radiation-hardened SAR ADC adopts delay-based double-feedback flip-flops to prevent soft errors which flips the data bits. Radiation-hardened IA and ADC were verified through compact model simulation, and fabricated CMOS chips were measured in radiation facilities to confirm their radiation tolerance.

• Journal of Korean Academy of Oral and Maxillofacial Radiology
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• v.25 no.2
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• pp.363-373
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• 1995

The aim of this study was to evaluate and compare observer performance between conventional radiographs and their digitized images for the detection of bone loss in the bifurcation of mandiblar first molar. One dried human mandible with minimal periodontal bone loss around the first molar was selected and serially enlarged 17 step defects were prepared in the bifurcation area. The mandible was radiographed with exposure time of 0.12, 0.20, 0.25, 0.32, 0.40, 0.64 seconds, after each successive step in the preperation and all radiographs were digitized with IBM-PC/32 bit-Dx compatible, video camera (VM-S8200, Hitachi Co., Japan), and color monitor(Multisync 3D, NEC, Japan). Sylvia Image Capture Board for the ADC(analog to digital converter) was used. The obtained results were as follows: 1. In the conventional radiographs, the mean score of the readability was higher at the condition of exposure time with 0.32 second. Also, as the size of artificial lesion was increased, the readability of radiographs was elevated (P<0.05). 2. In the digital images, the mean score of the readability was higher at the condition of exposure time with 0.40 second. Also, as the size of artificial lesion was increased, the readability of digital images was elevated(P<0.05). 3. At the same exposure time, the mean scores of readibility were mostly higher in the digitized images. As the exposure time was increased, the digital images were superior to radiographs in readability. 4. As the size of lesion was changed, the digital images were superior to radiographs in detecting small lesion. 5. The coefficient of variation of mean score has no significant difference between digital images and radiographs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.71-78
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• 2005

In this paper, we propose a transceiver for noncoherent OOK(On-Off Keying) Ultra Wide Band system based on magnitude detection. The proposed transceiver are designed using 0.18 micron CMOS technology and verified by simulation using SPICE and measurement. The proposed transceiver consist of parallelizer, Analog-to-Digital converter, clock generator, PLL and impulse generator. The time resolution of 1ns is obtained with 125MHz system clocks and 8x parallelization is carried out. The synchronized eight outputs with 2-bit resolution are delivered to the baseband. Impulse generator produces 1ns width pulse using digital CMOS gates. The simulation results and measurement show the feasibility of the proposed transceiver for UWB communication system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.83-91
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• 2014

This paper presents a capacitive readout circuit for tri-axes microaccelerometer with sub-fF offset calibration capability. A charge sensitive amplifier (CSA) with correlated double sampling (CDS) and digital to equivalent capacitance converter (DECC) is proposed. The DECC is implemented using 10-bit DAC, charge transfer switches, and a charge-storing capacitor. The DECC circuit can realize the equivalent capacitance of sub-fF range with a smaller area and higher accuracy than previous offset cancelling circuit using series-connected capacitor arrays. The readout circuit and MEMS sensing element are integrated in a single package. The supply voltage and the current consumption of analog blocks are 3.3 V and $230{\mu}A$, respectively. The sensitivities of tri-axes are measured to be 3.87 mg/LSB, 3.87 mg/LSB and 3.90 mg/LSB, respectively. The offset calibration which is controlled by 10-bit DECC has a resolution of 12.4 LSB per step with high linearity. The noise levels of tri-axes are $349{\mu}g$/${\sqrt}$Hz, $341{\mu}g$/${\sqrt}$Hz and $411{\mu}g$/${\sqrt}$Hz, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• ETRI Journal
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• v.32 no.2
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• pp.214-221
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• 2010

Radio frequency (RF) subsampling can be used by radio receivers to directly down-convert and digitize RF signals. A goal of a cognitive radio/software defined ratio (CR/SDR) receiver design is to place the analog-to-digital converter (ADC) as near the antenna as possible. Based on this, a band-pass sampling (BPS) frontend for CR/SDR is proposed and verified. We present a receiver architecture based second-order BPS and signal processing techniques for a digital RF frontend. This paper is focused on the benefits of the second-order BPS architecture in spectrum sensing over a wide frequency band range and in multiband receiving without modification of the RF hardware. Methods to manipulate the spectra are described, and reconstruction filter designs are provided. On the basis of this concept, second-order BPS frontends for CR/SDR systems are designed and verified using a hardware platform.